2 nm process

In semiconductor manufacturing, the "2 nm process" is the next MOSFET (metal–oxide–semiconductor field-effect transistor) die shrink after the "3 nm" process node.

The term "2 nanometer" or alternatively "20 angstrom" (a term used by Intel) has no relation to any actual physical feature (such as gate length, metal pitch or gate pitch) of the transistors. According to the projections contained in the 2021 update of the International Roadmap for Devices and Systems published by the Institute of Electrical and Electronics Engineers (IEEE), a "2.1 nm node range label" is expected to have a contacted gate pitch of 45 nanometers and a tightest metal pitch of 20 nanometers.

As such, "2 nm" is used primarily as a marketing term by the semiconductor industry to refer to a new, improved generation of chips in terms of increased transistor density (a higher degree of miniaturization), increased speed, and reduced power consumption compared to the previous "3 nm" node generation.

As of May 2022, TSMC was expected to begin risk "2 nm" production at the end of 2024 and mass production in 2025; Intel at that time forecasted production in 2024, and Samsung in 2025.

Background
By 2018, a number of transistor architectures had been proposed for the eventual replacement of FinFET, most of which were based on the concept of GAAFET: horizontal and vertical nanowires, horizontal nanosheet transistors (Samsung MBCFET, Intel Nanoribbon), vertical FET (VFET) and other vertical transistors,  complementary FET (CFET), stacked FET, several kinds of horizontal gate-all-around transistors such as nano-ring, hexagonal wire, square wire, and round wire gate-all-around transistors and negative-capacitance FET (NC-FET) which uses drastically different materials.

In late 2018, TSMC chairman Mark Liu predicted chip scaling would continue to "3 nm" and "2 nm" nodes; however, as of 2019, other semiconductor specialists were undecided as to whether nodes beyond "3 nm" could become viable. TSMC began research on "2 nm" in 2019 —expecting to transition from FinFET to GAAFET transistor type. In July 2021, TSMC received governmental approval to build its "2 nm" plant. In August 2020, it began building an R&D lab for "2 nm" technology in Hsinchu, expected to become partially operational by 2021. In September 2020, TSMC confirmed this and stated that it could also install production at Taichung depending on demand. According to the Taiwan Economic Daily (2020), expectations were for high yield risk production in late 2023. According to Nikkei, the company at that time expected to have been installing production equipment for "2 nm" by 2023.

Intel's 2019 roadmap scheduled potentially equivalent "3 nm" and "2 nm" nodes for 2025 and 2027, respectively, and in December 2019 announced plans for "1.4 nm" production in 2029.

At the end of 2020, seventeen European Union countries signed a joint declaration to develop their entire semiconductor industry, including developing process nodes as small as "2 nm", as well as designing and manufacturing custom processors, assigning up to €145 billion in funds.

In May 2021, IBM announced it had produced chips with "2 nm class" GAAFET transistors using three silicon layer nanosheets with a gate length of 12 nm.

In July 2021, Intel unveiled its process node roadmap from 2021 onwards. The company confirmed their "2 nm" process node called "Intel 20A", with the "A" referring to angstrom (a unit equivalent to 0.1 nanometers). At the same time, they introduced a new process node naming scheme that aligned their product names with similar designations from their main competitors. Intel's "20A" node was at that time projected to have been their first to move from FinFET to Gate-All-Around transistors (GAAFET); Intel's version was named 'RibbonFET'. Their 2021 roadmap scheduled the Intel "20A" node for volume production in 2024 and Intel "18A" for 2025.

In October 2021, at Samsung Foundry Forum 2021, Samsung announced it would start mass production with its MBCFET (multi-bridge channel FET, Samsung's version of GAAFET) "2 nm" process in 2025.

In April 2022, TSMC announced its GAAFET "N2" process technology would enter risk production phase at the end of 2024 and production phase in 2025. In July 2022, TSMC announced that its "N2" process technology was expected to feature backside power delivery and was expected to offer 10–15% higher performance at iso power or 20–30% lower power at iso performance and over 20% higher transistor density compared to N3E.

In July 2022, Samsung made a number of disclosures regarding the company's erstwhile forthcoming process technology called "2GAP" ("2nm Gate All-around Production"): the process erstwhile remained on track for 2025 launch into mass production; number of nanosheets was projected to increase from 3 in "3GAP" to 4; the company worked on several improvements of metallization, namely "single-grain metal" for low-resistance vias and direct-etched metal interconnect planned for "2GAP" and beyond.

In August 2022, a consortium of Japanese companies funded a new venture with government support called Rapidus for manufacturing of "2 nm" chips. Rapidus signed agreements with imec and IBM in December 2022.

In April 2023, at its Technology Symposium, TSMC introduced two more processes of its "2nm" technology platform: "N2P" featuring backside power delivery and scheduled for 2026 and "N2X" for high-performance applications. It was also revealed that ARM Cortex-A715 core fabbed on N2 process using high-performance standard library gained 16.4% of speed at iso power, saved 37.2% of power at iso speed, or gained ~10% of speed and saved ~20% of power simultaneously at iso voltage (0.8 V) compared to the core fabbed on N3E using 3-2 fin library.

Beyond 2 nm
In July 2021, Intel had planned "18A" production for 2025. Intel's February 2022 roadmap added that "18A" was erstwhile expected to have delivered 10% improvement in performance per watt compared to Intel "20A" and was planned to become manufacturing-ready in 2024 H2.

In December 2021, Vertical-Transport FET (VTFET) CMOS logic transistor design with a vertical nanosheet was demonstrated at sub-45 nm gate pitch.

In May 2022, imec presented a process technology roadmap which extends the current biannual cadence of node introduction and square-root-of-two node naming rule to 2036. The roadmap ends with process node "A2" (a metaphor for the concept of 2 angstroms), named by analogy with TSMC's naming scheme to be introduced by then.

Apart from dimensional scaling of transistor structures and interconnect, innovations forecast by imec were as follows:
 * transistor architecture (forksheet FET, CFET, CFET with atomic (2D material) channel);
 * deployment of high-NA (0.55) EUV tools with the first $400 million tool to be completed at ASML in 2023, and the first production tool to be shipped to Intel in 2025;
 * further reduction of standard cell height (eventually to "less than 4" tracks);
 * back-side power distribution, buried power rails;
 * new materials (ruthenium for metallization (interconnects), graphene, WS2 monolayer for atomic channel);
 * new manufacturing techniques (subtractive metallization, direct metal etch);
 * air gaps to further reduce relative permittivity of intermetal dielectric and, therefore, interconnect capacitance;
 * IC design innovations (2.5D chiplets, 3D interconnect), more advanced EDA tools.

In September 2022, Samsung presented their future business goals, which at that time included an aim to mass-produce "1.4 nm" by 2027.

As of 2023, Intel, TSMC and Samsung have all demonstrated CFET transistors. These transistors are made up of two stacked horizontal nanosheet transistors, one transistor is of the p-type (a pFET transistor) and the other transistor is of the n-type (an nFET transistor).