Communication-avoiding algorithm

Communication-avoiding algorithms minimize movement of data within a memory hierarchy for improving its running-time and energy consumption. These minimize the total of two costs (in terms of time and energy): arithmetic and communication. Communication, in this context refers to moving data, either between levels of memory or between multiple processors over a network. It is much more expensive than arithmetic.

Two-level memory model
A common computational model in analyzing communication-avoiding algorithms is the two-level memory model:


 * There is one processor and two levels of memory.
 * Level 1 memory is infinitely large. Level 0 memory ("cache") has size $$M$$.
 * In the beginning, input resides in level 1. In the end, the output resides in level 1.
 * Processor can only operate on data in cache.
 * The goal is to minimize data transfers between the two levels of memory.

Matrix multiplication
Corollary 6.2:

More general results for other numerical linear algebra operations can be found in. The following proof is from.

$$

Motivation
Consider the following running-time model:

⇒ Total running time = γ·(no. of FLOPs) + β·(no. of words)
 * Measure of computation = Time per FLOP = γ
 * Measure of communication = No. of words of data moved = β

From the fact that β >> γ as measured in time and energy, communication cost dominates computation cost. Technological trends indicate that the relative cost of communication is increasing on a variety of platforms, from cloud computing to supercomputers to mobile devices. The report also predicts that gap between DRAM access time and FLOPs will increase 100× over coming decade to balance power usage between processors and DRAM.

Energy consumption increases by orders of magnitude as we go higher in the memory hierarchy.

United States president Barack Obama cited communication-avoiding algorithms in the FY 2012 Department of Energy budget request to Congress: "New Algorithm Improves Performance and Accuracy on Extreme-Scale Computing Systems. On modern computer architectures, communication between processors takes longer than the performance of a floating-point arithmetic operation by a given processor. ASCR researchers have developed a new method, derived from commonly used linear algebra methods, to minimize communications between processors and the memory hierarchy, by reformulating the communication patterns specified within the algorithm. This method has been implemented in the TRILINOS framework, a highly-regarded suite of software, which provides functionality for researchers around the world to solve large scale, complex multi-physics problems."

Objectives
Communication-avoiding algorithms are designed with the following objectives:


 * Reorganize algorithms to reduce communication across all memory hierarchies.
 * Attain the lower-bound on communication when possible.

The following simple example demonstrates how these are achieved.

Matrix multiplication example
Let A, B and C be square matrices of order n × n. The following naive algorithm implements C = C + A * B:

for i = 1 to n     for j = 1 to n          for k = 1 to n              C(i,j) = C(i,j) + A(i,k) * B(k,j)

Arithmetic cost (time-complexity): n2(2n − 1) for sufficiently large n or O(n3).

Rewriting this algorithm with communication cost labelled at each step

for i = 1 to n     {read row i of A into fast memory}               - n2 reads for j = 1 to n         {read C(i,j) into fast memory}               - n2 reads {read column j of B into fast memory}       - n3 reads for k = 1 to n             C(i,j) = C(i,j) + A(i,k) * B(k,j) {write C(i,j) back to slow memory}          - n2 writes

Fast memory may be defined as the local processor memory (CPU cache) of size M and slow memory may be defined as the DRAM.

Communication cost (reads/writes): n3 + 3n2 or O(n3)

Since total running time = γ·O(n3) + β·O(n3) and β >> γ the communication cost is dominant. The blocked (tiled) matrix multiplication algorithm reduces this dominant term:

Blocked (tiled) matrix multiplication
Consider A, B and C to be n/b-by-n/b matrices of b-by-b sub-blocks where b is called the block size; assume three b-by-b blocks fit in fast memory.

for i = 1 to n/b for j = 1 to n/b {read block C(i,j) into fast memory}          - b2 × (n/b)2 = n2 reads for k = 1 to n/b {read block A(i,k) into fast memory}      - b2 × (n/b)3 = n3/b reads {read block B(k,j) into fast memory}      - b2 × (n/b)3 = n3/b reads C(i,j) = C(i,j) + A(i,k) * B(k,j)         - {do a matrix multiply on blocks} {write block C(i,j) back to slow memory}      - b2 × (n/b)2 = n2 writes

Communication cost: 2n3/b + 2n2 reads/writes << 2n3 arithmetic cost

Making b as large possible:
 * 3b2 ≤ M

we achieve the following communication lower bound:
 * 31/2n3/M1/2 + 2n2 or Ω (no. of FLOPs / M1/2)

Previous approaches for reducing communication
Most of the approaches investigated in the past to address this problem rely on scheduling or tuning techniques that aim at overlapping communication with computation. However, this approach can lead to an improvement of at most a factor of two. Ghosting is a different technique for reducing communication, in which a processor stores and computes redundantly data from neighboring processors for future computations. Cache-oblivious algorithms represent a different approach introduced in 1999 for fast Fourier transforms, and then extended to graph algorithms, dynamic programming, etc. They were also applied to several operations in linear algebra  as dense LU and QR factorizations. The design of architecture specific algorithms is another approach that can be used for reducing the communication in parallel algorithms, and there are many examples in the literature of algorithms that are adapted to a given communication topology.