Draft:Crestmont (microarchitecture)

Crestmont is the codename for Intel's fifth generation out of order Atom microarchitecture, and is the successor to Gracemont. It is used as the efficient-core and low power efficient-core microarchitecture in Intel's first generation Core Ultra processors (codenamed "Meteor Lake"), and Xeon 6 E-core processors (codenamed "Sierra Forest").

Design
Crestmont contains the following enhancements over Gracemont:
 * 6 wide rename and dispatch, compared to 5-wide in Gracemont
 * 6144 entry L2 Branch Target Buffer, compared to 5120 in Gracemont
 * Branch predictor can scan 128 bytes per cycle, compared to 32 bytes per cycle in Gracemont
 * Renamer can eliminate more µops by itself
 * Floating point divide latency reduced to 5 cycles, from 10 in Gracemont
 * Floating point scheduler sizes increased to a total of 60 entries, from 55 in Gracemont
 * L2 TLB size increased to 3072 entries with 6-way associativity, from 2048 entries with 4-way associativity

Technology

 * Manufactured on Intel 4 (Meteor Lake compute tile), Intel 3 (Sierra Forest compute tile) , or TSMC N6 (Meteor Lake SoC tile)
 * 2 three-wide decoders in a cluster, each capable of fetching 32 bytes per cycle from the instruction cache
 * 6-wide rename/dispatch
 * 256 entry reorder buffer
 * 17 execution ports with distributed schedulers
 * 32 kilobyte L1 data cache with eight-way associativity and 3 cycle latency
 * 64 kilobyte L1 instruction cache with eight-way associativity
 * 2-4 megabyte L2 cache with sixteen-way associativity and 17 cycles of latency shared between up to four cores
 * Access to shared L3 cache with P-cores or other E-core modules on Meteor Lake and Sierra Forest