File talk:Pipeline MIPS.png

Poor image
My apologies to whoever created this image, but it's really not very good. I understand that it's only meant to provide an overview of the architecture, but there are somethings about it that are unnecessarily confusing, and possibly wrong.
 * The inputs and outputs from the inter-stage registers are all misaligned. It's not at all clear what outputs correspond to what inputs, and, at least in the case of the ID/EX register, the number of outputs does not match the number of inputs.
 * I don't think the actions of the PC (green "Address" register on far left) are correct: the way it's set up, it appears that the same instruction will get executed 4 times before the incremented PC value gets back from the fourth stage.
 * I question whether the write back data/addr/enable signals really go mux to input, without being registered? Unless the register file is clocked (which leads to other timing problems), then I think these signals need to be clocked.

I haven't looked at MIPS specifically in several years, so please correct me if I'm wrong.  B. Mearns * , KSC 16:57, 3 June 2008 (UTC)