High-level verification

High-level verification (HLV), or electronic system-level (ESL) verification, is the task to verify ESL designs at high abstraction level, i.e., it is the task to verify a model that represents hardware above register-transfer level (RTL) abstract level. For high-level synthesis (HLS or C synthesis), HLV is to HLS as functional verification is to logic synthesis.

Electronic digital hardware design has evolved from low level abstraction at gate level to register transfer level (RTL), the abstraction level above RTL is commonly called high-level, ESL, or behavioral/algorithmic level.

In high-level synthesis, behavioral/algorithmic designs in ANSI C/C++/SystemC code is synthesized to RTL, which is then synthesized into gate level through logic synthesis. Functional verification is the task to make sure a design at RTL or gate level conforms to a specification. As logic synthesis matures, most functional verification is done at the higher abstraction, i.e. at RTL level, the correctness of logic synthesis tool in the translating process from RTL description to gate netlist is of less concern today.

High-level synthesis is still an emerging technology, so High-level verification today has two important areas under development
 * 1) to validate HLS is correct in the translation process, i.e. to validate the design before and after HLS are equivalent, typically through formal methods
 * 2) to verify a design in ANSI C/C++/SystemC code is conforming to a specification, typically through logic simulation.

Product areas

 * Formal Solution: Verify high level models against RTL designs
 * Simulation Solution: Intelligent stimulus generation, code and functional coverage, temporal assertion checker