Jaguar (microarchitecture)

The AMD Jaguar Family 16h is a low-power microarchitecture designed by AMD. It is used in APUs succeeding the Bobcat Family microarchitecture in 2013 and being succeeded by AMD's Puma architecture in 2014. It is two-way superscalar and capable of out-of-order execution. It is used in AMD's Semi-Custom Business Unit as a design for custom processors and is used by AMD in four product families: Kabini aimed at notebooks and mini PCs, Temash aimed at tablets, Kyoto aimed at micro-servers, and the G-Series aimed at embedded applications. Both the PlayStation 4 and the Xbox One use SoCs based on the Jaguar microarchitecture, with more powerful GPUs than AMD sells in its own commercially available Jaguar APUs.

Design

 * 32 KiB instruction + 32 KiB data L1 cache per core, L1 cache includes parity error detection
 * 16-way, 1–2 MiB unified L2 cache shared by two or four cores, L2 cache is protected from errors by the use of error correcting code
 * Out-of-order execution and speculative execution
 * Integrated memory controller
 * Two-way integer execution
 * Two-way 128-bit wide floating-point and packed integer execution
 * Integer hardware divider
 * Consumer processors support two DDR3L DIMMs in one channel at frequencies up to 1600 MHz
 * Server processors support two DDR3 DIMMs in one channel at frequencies up to 1600 MHz with ECC
 * As a SoC (not just an APU) it integrates Fusion controller hub
 * Jaguar does not feature clustered multi-thread (CMT), meaning that execution resources are not shared between cores

Instruction-set support
The Jaguar core has support for the following instruction sets and instructions: MMX, SSE, SSE2, SSE3, SSSE3, SSE4a, SSE4.1, SSE4.2, AVX, F16C, CLMUL, AES, BMI1, MOVBE (Move Big-Endian instruction), XSAVE/XSAVEOPT, ABM (POPCNT/LZCNT), and AMD-V.

Improvements over Bobcat

 * Over 10% increase in clock frequency
 * Over 15% improvement in instructions per clock (IPC)
 * Added support for SSE4.1, SSE4.2, AES, CLMUL, MOVBE, AVX, F16C, BMI1
 * Up to four CPU cores
 * L2 cache is shared between cores
 * FPU datapath width increased to 128-bit
 * Added hardware integer divider
 * Enhanced cache prefetchers
 * Doubled bandwidth of load–store units
 * C6 and CC6 low power states with lower entry and exit latency
 * Smaller, 3.1 mm2 area per core
 * Integrated Fusion controller hub (FCH)
 * Video Coding Engine

Desktop
SoCs using Socket AM1:

Jaguar derivative and successor
In 2017, a derivative of the Jaguar microarchitecture was announced in the APU of Microsoft's Xbox One X (Project Scorpio) revision to the Xbox One. The Project Scorpio APU is described as a 'customized' derivative of the Jaguar microarchitecture, utilizing eight cores clocked at 2.3 GHz.

The Puma successor to Jaguar was released in 2014 and targeting entry level notebooks and tablets.