Low power flip-flop

Low power flip-flops are flip-flops that are designed for low-power electronics, such as smartphones and notebooks. A flip-flop, or latch, is a circuit that has two stable states and can be used to store state information.

Motivation
In most VLSI devices, a large portion of power dissipation is due to the clock network and clocked sequential elements, which can account for anywhere between 25% - 40% of the total power in a design. Sequential elements, latches, and flip-flops dissipate power when there is switching in their internal capacitance. This may happen with every clock transition/pulse into the sequential element. Sometimes the sequential elements need to change their state, but sometimes they retain their state and their output remains the same, before and after the clock pulse. This leads to unnecessary dissipation of power due to clock transition. If flip-flops are designed in such a way that they are able to gate the clock with respect to their own internal data path, power dissipation can be brought down.

Conditional pre-charging


This technique is used for controlling the internal node in the pre charging path in a sequential element. In the above circuit, the D input is connected to the first NMOS in the PDN network (CMOS). When this input is high, the output should also be high. The clk input to the PMOS will charge the output node to high when clk is low. If the D input is already high, there is no need to charge the output to high again. Thus, if one can control this behaviour there can be a power reduction in the flip-flop. To control the internal node in the precharge path, a control switch is used as shown in Fig 1. Only a transition that is going to change the state of the output is allowed. As one of the input to flops is the clock, considering the clock (Clock signal) is the element that makes the most transition in a system, a technique such as conditional precharging can significantly help reduce power.

Conditional capture


This technique looks to prevent any necessary internal node transition by looking at the input and output and checking to see if there is a need to switch states. In this circuit, there is a control signal that is applied to control the switching of the internal nodes. We can see the clock is supplied to two NMOS in series. The discharge path will not be complete until the control signal allows the last NMOS to be on. This control signal could be generated by a simple circuit, with its inputs being the present output, input and the state of the clock (high or low). If the output of the flip-flop is low, and a high clock pulse is applied with the input being a low pulse, then there is no need for a state transition. The extra computation to sample the inputs cause an increase in setup time of the flip-flop; this is a disadvantage of this technique. A further insight into this technique has been explained well in the journal "High-Performance and Low-Power Conditional Discharge Flip-Flop" by Tarek K. Darwish and Magdy A. Bayoumi.

Data transition look-ahead
In Fig3, the circuit shows how the data transition technique can be beneficial for power saving. The XNOR logical function is performed on the input of the D flip-flop and the output Q. When Q and D are equal, output of the logical XNOR will be zero, generating no internal clock. The circuit can be broken down into 3 parts: data-transition look ahead, pulse generator, and clock generator. The pulse generator output is fed into the clock generator which is used to clock the D flip-flop. Based on the input and output signals, if there is a need to change the state of the D flip-flop, then the clock is allowed to switch to cause a transition; else, the clock is not allowed to transition. When the clock does not make a transition, some time has been already spent in computing the logic, and data from the D input may make it through the first stage of the flip-flop, consuming some power. This power consumption is still less than what an ordinary flipflop would have consumed with a clock transition and no change in output.

Clock on demand
Fig4 shows the clock on demand technique. The clock generator and pulse generator are combined in this implementation. The advantage of this is that there is reduction in area, improving energy efficiency. If the XNOR output is zero, then the pulse generator will not generate any internal signal from the external clock. If the output Q and input D do not match then the pulse generator will generate an internal clock to trigger a state transition.