Mano machine

The Mano machine is a computer theoretically described by M. Morris Mano. It contains a central processing unit, random access memory, and an input-output bus. Its limited instruction set and small address space limit it to use as a microcontroller, but it can easily be expanded to have a 32-bit accumulator register, and 28-bit addressing using a hardware description language like Verilog or VHDL; and at the same time, make room for new instructions.

Characteristics
The Mano machine is similar in many respects to the PDP-8, such as the same address space, only one accumulator register, and many similar instructions. The Mano machine has a 4096x16 shared data/program memory segment requiring a 12-bit address bus. The data bus is 16 bits. There are 8-bit input/output buses for external communication, and associated interrupt flags.

There is one 16-bit accumulator register, and single-bit registers (latches) for addition carry and system halt.

Instruction set
There are 25 instructions that fall into 3 categories: direct / indirect memory referencing operations, register referencing operations, and input/output/interrupt operations.

Each instruction is 16 bits long [4 nybbles, or 1 word]. This means that memory referencing instructions contain 4 bits of op-code data, and 12 bits dedicated to the address.

Applications to computer optimization theory
The machine specifications include a finite state machine that determines the processor's micro-operations. The canonical implementation of the state machine is an excellent candidate for reduction, and can also be re-implemented as a pipelined processor.