Nader Bagherzadeh

Nader Bagherzadeh is a professor of computer engineering in the Department of Electrical Engineering and Computer Science at the University of California, Irvine, where he served as a chair from 1998 to 2003. Bagherzadeh has been involved in research and development in the areas of: Computer Architecture, Reconfigurable Computing, VLSI Chip Design, Network-on-Chip, 3D chips, Sensor Networks, Computer Graphics, Memory and Embedded Systems. Bagherzadeh was named Fellow of the Institute of Electrical and Electronics Engineers (IEEE) in 2014 for contributions to the design and analysis of coarse-grained reconfigurable processor architectures. Bagherzadeh has published more than 400 articles in peer-reviewed journals and conferences. He was with AT&T Bell Labs from 1980 to 1984.

Education

 * Ph.D., 1987 Computer Engineering University of Texas-Austin
 * M.Sc., 1979 Electrical Engineering University of Texas-Austin
 * B.Sc., 1977 Electrical Engineering University of Texas-Austin

Notable works

 * MorphoSys: an integrated reconfigurable system for data-parallel and computation-intensive applications
 * Design and implementation of the MorphoSys reconfigurable computing processor
 * Power-aware scheduling under timing constraints for mission-critical embedded systems
 * Optimal Ring Embedding in Hypercubes with Faulty Links
 * A scalable register file architecture for dynamically scheduled processors
 * A framework for reconfigurable computing: task scheduling and context management
 * Performance study of a multithreaded superscalar microprocessor

Awards

 * 2014, Khwarizmi International Award (27th Session)
 * 2002, Best paper award in IEEE Transactions on VLSI Design (TVLSI)
 * 2002, Best paper award in the proceedings of Asia and South Pacific Design Automation Conference (ASPDAC)