Ne-XVP

Ne-XVP was a research project executed between 2006-2008 at NXP Semiconductors. The project undertook a holistic approach to define a next generation multimedia processing architecture for embedded MPSoCs that targets programmability, performance scalability, and silicon efficiency in an evolutionary way. The evolutionary way implies using existing processor cores such as NXP TriMedia as building blocks and supporting industry programming standards such as POSIX threads. Based on the technology-aware design space exploration, the project concluded that hardware accelerators facilitating task management and coherency coupled with right dimensioning of compute cores deliver good programmability, scalable performance and competitive silicon efficiency.

Research
Ne-XVP's research subjects and corresponding publications:
 * 1) Asymmetric multicore architecture with generic accelerators
 * 2) Hardware multithreading in VLIWs
 * 3) Low-complexity cache coherence
 * 4) Hardware accelerators for task scheduling and synchronization:
 * 5) A Hardware Task Scheduler
 * 6) Hardware Synchronization Unit to sync threads
 * 7) Task Management Unit
 * 8) Instruction cache sharing
 * 9) Design Space Exploration with Performance Density as the optimization function
 * 10) Technology modeling for embedded processors
 * 11) Parallelization of complex multimedia algorithms (H.264, Frame Rate Conversion)
 * 12) Auto-parallelizing compilers
 * 13) Time-aware programming languages in cooperation with the ACOTES project
 * 14) Visual programming
 * 15) Task-level speculation
 * 16) Porting GCC to Exposed Pipeline VLIW Processors
 * 17) Multiprogram workload for embedded processing
 * 18) A 1-GHz embedded VLIW processor

Project members

 * Ghiath Al-Kadi
 * Zbigniew Chamski
 * Dmitry Cheresiz
 * Marc Duranton (project leader)
 * Surendra Guntur
 * Jan Hoogerbrugge
 * Anirban Lahiri
 * Ondrej Popp
 * Andrei Terechko
 * Alex Turjan
 * Clemens Wust