Puma (microarchitecture)

The Puma Family 16h is a low-power microarchitecture by AMD for its APUs. It succeeds the Jaguar as a second-generation version, targets the same market, and belongs to the same AMD architecture Family 16h. The Beema line of processors are aimed at low-power notebooks, and Mullins are targeting the tablet sector.

Design
The Puma cores use the same microarchitecture as Jaguar, and inherits the design:
 * Out-of-order execution and Speculative execution, up to 4 CPU cores
 * Two-way integer execution
 * Two-way 128-bit wide floating-point and packed integer execution
 * Integer hardware divider
 * Puma does not feature clustered multi-thread (CMT), meaning that there are no "modules"
 * Puma does not feature Heterogeneous System Architecture or zero-copy
 * 32 KiB instruction + 32 KiB data L1 cache per core
 * 1–2 MiB unified L2 cache shared by two or four cores
 * Integrated single channel memory controller supporting 64bit DDR3L
 * 3.1 mm2 area per core

Instruction set support
Like Jaguar, the Puma core has support for the following instruction sets and instructions: MMX, SSE, SSE2, SSE3, SSSE3, SSE4a, SSE4.1, SSE4.2, AVX, F16C, CLMUL, AES, BMI1, MOVBE (Move Big-Endian instruction), XSAVE/XSAVEOPT, ABM (POPCNT/LZCNT), and AMD-V.

Improvements over Jaguar

 * 19% CPU core leakage reduction at 1.2V
 * 38% GPU leakage reduction
 * 500 mW reduction in memory controller power
 * 200 mW reduction in display interface power
 * Chassis temperature aware turbo boost
 * Selective boosting according to application needs (intelligent boost)
 * Support for ARM TrustZone via integrated Cortex-A5 processor
 * Support for DDR3L-1866 memory

Puma+
AMD released a revision of Puma microarchitecture, Puma+, updating the video decoder from UVD 4.2 to 6.0 and the video encoder from VCE 2.0 to VCE 3.1.

Features
APU features table