RISC5

RISC5 may refer to one of two different open instruction set architectures:


 * The RISC5 instruction set and CPU designed by Niklaus Wirth for Project Oberon, nominally run in synthesized form on an FPGA as part of the OberonStation package


 * The RISC-V instruction set architecture derived from designs that originated at University of California, Berkeley, and supported by multiple vendors aiming for mass chip production