STM8

The STM8 is an 8-bit microcontroller family by STMicroelectronics. The STM8 microcontrollers use an extended variant of the ST7 microcontroller architecture. STM8 microcontrollers are particularly low cost for a full-featured 8-bit microcontroller.

Architecture
The STM8 is very similar to the earlier ST7, but is better suited as a target for C due to its 16-bit index registers and stack pointer-relative addressing mode. Although internally a Harvard architecture it has "memory bridge" that creates a unified 24-bit address space, allowing code to execute out of RAM (useful for in-system programming of the flash ROM), and data (such as lookup tables) to be accessed out of ROM. On access the "memory bridge" stalls the CPU if required so that RAM-like write access to the flash ROM is possible. Code execution from the EEPROM is denied and creates a reset event. Random access to data above 64K is limited to special "load far" instructions; most operations' memory operands can access at most 128K (a 16-bit base address plus 16-bit offset).

Depending on the device type, the amount of RAM is in the range of 1 to 6 KiB, and the amount of ROM is 4 to 8 KiB (Low density), 16 to 32 KiB (Medium density), or 32 to 96 KiB (High density).

It has the same six registers (A, X, Y, SP, PC, CC) as the ST7, but the index registers X and Y have been expanded to 16 bits, and the program counter has been expanded to 24 bits. The accumulator A and the stack pointer remain 8 and 16 bits, respectively.

The condition code register has two more defined bits, for a total of seven. There is an overflow flag, and a second interrupt enable bit, allowing four interrupt priority levels.

Subfamilies

 * STM8AF automobile
 * STM8AL automobile low-power
 * STM8L low-power
 * STM8S general purpose
 * STM8T touch-sensing
 * STLUX lighting control
 * STNRG Pulse-width modulation-controllers

Compiler support
The STM8 is supported by the free Small Device C Compiler, the free of charge closed source Cosmic C compiler, and the non-free IAR C and Raisonance compilers. Besides C there is the open-source STM8 eForth, an interactive Forth system for the STM8.

Changes compared to ST7
The STM8 instruction set is mostly a superset of the ST7's, but it is not completely binary compatible.

Operations on the X and Y registers are extended to 16 bits. Thus, loads and stores access two bytes of memory rather than one. (Also, the half-carry flag has been changed to reflect the carry from bit 7 to bit 8 of the 16-bit result, rather than the carry from bit 3 to 4.)

Interrupts push nine bytes of state instead of five as on the ST7.

The multiply instruction stores the 16-bit product in the specified index register (e.g. X), rather than dividing it between X and A.

Indirect addressing modes which fetch an 8-bit address from memory (opcodes,  ,  ,  ,  ,  , and  ) have been deleted; all indirect addressing modes fetch 16-bit addresses. A new prefix byte  has been added, and used to encode indirect starting with a 16-bit address.

The bit manipulation instructions have been changed to take a 16-bit address and to require the  prefix byte. The unprefixed opcodes  and   they formerly occupied are instead used for stack-pointer relative addressing.

Some rarely used branch instructions have had their opcodes changed to require a  prefix, and the unprefixed opcodes reassigned to signed branches which depend on the V flag.

Load and compare instructions targeting the X register are of little use on the ST7 with addressing modes indexed by the X register. On the STM8, when such operations specify a memory operand indexed by the X register, the register operand is changed to Y. With a   prefix, the registers are reversed so the index register is Y and the operand register is X.

One major performance difference is that the STM8 fetches 32 bits from ROM per cycle, and many instructions take one cycle to execute. Depending in the instruction length and the number of cycles needed execution from RAM is somewhat slower. The ST7, in contrast, fetches 8 bits per cycle and takes one cycle per instruction byte.

Instruction set
Most STM8 opcode bytes consist of 1 bit of type (one- or two-operand), three bits of addressing mode, and four bits of opcode. Only 6 addressing modes and 12 one-operand opcodes are assigned, leaving encoding space where other instructions are placed.

STM8 instructions consist of an optional prefix byte (, ,  , or  ), an opcode byte, and a few (up to four, but rarely more than two) bytes of operands. Prefix bytes mostly modify the addressing mode used to specify the memory operand, but in some cases, prefixes  and   change the meaning of the opcode byte completely.

Prefix  exchanges X and Y in the following instruction. In the table below, these variants are combined on one line by writing "X/Y", which means either "X" or "Y". Prefix  is also used in two places to introduce new opcodes: the BCPL and BCCM instructions, and some branch conditions.

Prefix  converts instructions with an offset operand (addr16,X) to indirect addressing ([addr8],X). The offset is replaced by the 8-bit address of a 16-bit offset value in memory. It is used only for this function.

Prefix  has both of the preceding effects, converting (addr16,X) addressing modes to ([addr8],Y).

Prefix  is used in a number of places, in a much less regular pattern. In some cases, it introduces new addressing modes (particularly an ([addr16],X) 16-bit indirect mode), but it also introduces many completely new operations.

For CPW and LDW instructions where the operand addressing mode is indexed by X, the STM8 uses the Y register by default instead of X. Applying a   prefix exchanges X and Y so the register is X and the addressing mode is indexed by Y.