Talk:Apple A7

64-bit tools (LLVM) not ready(?!) - for months?
From an Apple guy: http://lists.cs.uiuc.edu/pipermail/llvmdev/2013-September/065480.html

http://www.phoronix.com/scan.php?page=news_item&px=MTQ1ODM

is GCC usable instead (or other compiler)? Not sure is allowed (in the Appstore) since it's GPLv3. comp.arch (talk) 12:15, 11 September 2013 (UTC)

the LLVM in XCode is ready, it's the version in llvm.org is not ready. PH007 (talk) 16:42, 11 September 2013 (UTC)


 * It looks to me like there's two different implementations of ARMv8 support in LLVM, one done in the open and not quite ready for production work unlike the gcc one, and an independent one done secretly by Apple which was used in production, and now there's the bother of merging them. Might lead to a better implementation overall I guess. Dmcq (talk) 11:04, 13 September 2013 (UTC)

Quad-core?
Where does it say that the Apple A7 is a quad-core chip? Apple didn't say anything about that, only that it is 64-bit and that it contains 1 billion transistors. Giggett (talk) 19:50, 11 September 2013 (UTC)


 * 1b transistors in 102mm2 is not a small feat either. for comparison, i7-4770 4 core comes in 1.4b and 177mm2. apple is able to pack 25% more transistors in the same area than intel with 22nm. — Preceding unsigned comment added by 152.135.235.188 (talk) 20:49, 11 September 2013 (UTC)


 * Yeah I know, I just want to know where you got that info from, and not just made it up. Giggett (talk) 04:36, 12 September 2013 (UTC)


 * This is a mobile device with a relatively small battery, it's very likely, drawing upon Apple performance comparisons and power consumption that this is an ARM big.LITTLE processor, featuring two Cortex-A57 and two Cortex-A53 processors (or a custom Apple equivalent). Refer to the Samsung Exynos Octa for an existing example in the mobile market. Looking at other wiki pages, this would be refered to as dual core + dual core.86.167.39.107 (talk) 14:18, 12 September 2013 (UTC)


 * A57 and A15 are similar and most dual-core A15 I'd seen didn't have big.LITTLE integrated. For example Exynos 5250 or TI OMAP 5. And apple use its own microarchitecture on top of armv8, which make it unlikely to support arm's big.little just as you won't find any snapdragon krait cpu have big.little support
 * Besides, I don't think Apple would only claim a 2x cpu performance increase if it have doubled its count on cpu core, other than the increase in cpu frequency and the switch from 32 bit to 64 bit plus improvements in instruction set.C933103 (talk) 04:53, 13 September 2013 (UTC)


 * Probably most of that chip is cache memory and the GPUs and other special circuitry. It sounds to me like the Apple A7 has a greater disparity between 32 bit speed and 64 bit speed than ARM were talking about for ARM's A57 so I'd guess it is an Apple own design. Otherwise why try encouraging app developers to use the 64 bit tools so generally? For straightforward work not involving lots of floating point work and with no great need for speed the A57 would give some increase but you'd have to weigh it against the bother of having another version for the older platforms. Dmcq (talk) 11:13, 13 September 2013 (UTC)

incorp 2GB memory?
No matter that's POP packing or PIP packaging, those memory aren't incorporated in the processor chip, right? C933103 (talk) 05:02, 13 September 2013 (UTC)
 * Yep. You can't fit 16 billion bits into 1 billion transistors. They'd stick a memory chip on top like in the A6. Dmcq (talk) 11:18, 13 September 2013 (UTC)
 * In fact I don't know how many bits but 8 billion if 1 gigabyte. Dmcq (talk) 23:32, 15 September 2013 (UTC)
 * The RAM is not a part of the SoC-die, but it is incorporated in the POP. We know this since we have photos of the tiny motherboard and there's no additional space for RAM on it. I don't think it's an issue sticking 2 GB into the POP, but that doesn't mean that they did so . -- Henriok (talk) 07:36, 16 September 2013 (UTC)

Is Apple A7 still samsung-made?
http://www.macobserver.com/tmo/article/apple-excludes-samsung-from-a7-chip-manufacturing and http://www.padgadget.com/2013/03/12/intel-rumored-to-make-10-percent-of-apple-a7-chips-while-samsung-gets-cut-by-half/ C933103 (talk) 05:04, 13 September 2013 (UTC)

Producing since sept2013?
Isn't there reports saying production started weeks before announcement?C933103 (talk) 04:40, 15 September 2013 (UTC)
 * Actually. The earliest pictures of A7 prototypes are from week 42, 2012 and the A7 in Apple's promo video is from week 34, 2013 (19-25 August). The consensus though is to use the date from which the processors are shipping in actual products. -- Henriok (talk) 11:33, 15 September 2013 (UTC)

Section on speculation
An editor removed the "Unconfirmed features and speculation" section with the claim that "Speculation is unwelcome in wikipedia". I can sympathize with decision to remove the section, but they may not have understood that the section was created by Henriok in response to other editors persistently adding "facts" about memory, cores, GPU, MHz, process, or manufacturer without realizing that they were basing these additions on rumors and speculation.

Until someone tears down an iPhone 5s, puts it through its paces, and uncaps the A7, we're not going to have a good source for those details on the A7. I think Henriok's solution of moving the speculative facts to their own section was a good compromise between the low-level edit warring going on between the editors who wanted to put those "facts" in the article and those who wanted to leave the article free of those "facts" (full-disclosure: I came down on the side of those who wanted the article free of the speculative facts). While it is true that speculation in articles by WP editors is unwelcome in WP, it is quite common for WP articles to summarize or otherwise take note of the speculations of analysts and the media.

I'd like for the section to be restored (although I would be comfortable removing it as extraneous once we have confirmed details). —RP88 (talk) 21:04, 17 September 2013 (UTC)


 * Thanks! That's exactly the reason why I put the section there. Add to that, rampant speculation about Apple minutia is a fact and I provided plenty of references for every non confirmed statement I put in the list. The section wasn't speculative on its own, it was reporting on the speculation that was and that should pass Wikipedia's rules. -- Henriok (talk) 06:58, 18 September 2013 (UTC)

Ha, it looks like this might be a moot issue. Anand Lal Shimpi has released his review of the iPhone 5s and it includes copious details about the A7. While he does still have some speculation in his review, it's at least informed speculation, as he has his hands on an iPhone 5s and is able to run benchmarking apps and custom code on it to figure out it's features. —RP88 (talk) 07:13, 18 September 2013 (UTC)


 * [moved below in a new section] comp.arch (talk) 09:03, 19 September 2013 (UTC)
 * Series6 GPU discussion moved to, below. —RP88 (talk) 14:14, 22 September 2013 (UTC)

First consumer ARM based SoC
The lead intro has the following sentence:
 * Furthermore, AnandTech makes the claim that the A7 chipset "is the world's first consumer ARM based [system-on-a-chip] with 64-bit support."

I think that sentence could be left as it is, however, it has attracted some attention from editors. I don't know if the claim is accurate, and I haven't seen it made by anyone other than AnandTech (but they're generally quite reliable and I have no trouble believing them). Has anyone seen someone else making the same claim as AnandTech, or disputing their claim? If the claim in uncontroversial, the sentence in the intro could be replaced with the following:
 * The A7 is the world's first consumer ARM based system on a chip with 64-bit support.

—RP88 (talk) 21:23, 17 September 2013 (UTC)

Secure Enclave via TrustZone/SecureCore
The article currently says that A7's Secure Enclave implements TrustZone/SecureCore. I'm not convinced that this is correct. The reference for the statement seems kind of speculative. It's not apparent to me that the person who posted that answer to Quora either has actual knowledge of the iPhone 5s/A7 chip or is a reliable source of informed speculation. —RP88 (talk) 09:20, 18 September 2013 (UTC)
 * It is a standard part of the ARMv8 architecture and I can't see why they would scrimp on implementing it properly as it helps with privacy and combating piracy. Dmcq (talk) 10:57, 18 September 2013 (UTC)
 * Yes, but TrustZone & SecureCore are also standard parts of the ARMv7 architecture, which Apple SoCs have used since the iPhone 3GS. So part of the point I was trying to make, and perhaps I wasn't very clear, is (1) is the new Secure Enclave implemented via the standard TrustZone/SecureCore technology that's been around awhile, or (2) is the new Secure Enclave technology some sort of reimplementation of TrustZone/SecureCore (as the current wording implies). —RP88 (talk) 11:58, 18 September 2013 (UTC)
 * You're wondering if Apple have decided to ignore the ARM way of doing it and are doing something of their own is that what you are saying? That would certainly be a big black mark against the ARM design but I can't see any reason to even speculate it at the moment. Dmcq (talk) 15:38, 18 September 2013 (UTC)
 * Reading that article again it does talk about having special hardware for secure enclave. Normally special hardware is needed only when there is a possibility of someone hacking into the address and data lines while the secure monitor is working and then you have to have fast encryption and decryption for them like in some games machines.. Dmcq (talk) 16:04, 18 September 2013 (UTC)

Not Apple-designed(?)
ARMv8 is a *different* ISA can't be derived from ARMv7-derived Swift. Anand is probably wrong when he says: "The CPU cores are, once again, a custom design by Apple. [..] but rather some evolution of Apple’s own Swift architecture".

Anand says in one review "Cyclone is a 64-bit ARMv8 core and not some Apple designed ISA.". Microarchitecture must implement this *not* Apple-designed ISA. And nothing I've seen says it is their custom microarchitecture, except Anand denying it. Since it is the first publicly available ARMv8-based core that we know of, then we can't compare timings to see that some instructions are implemented differently. I think it's just ARM's Cortex-A57 or A53 and noone can prove otherwise at this point(?) Do they even have an architectural license to the ARMv8? They have one for the ARMv7, I don't remember seeing they have to the ARMv8. Since it's a new version and a major update - a different *ISA* I'm sure you need a new one, a more expensive one. That is however just my speculation. I say to much speculation that the core is Apple-designd and need some confirmation. comp.arch (talk) 09:09, 19 September 2013 (UTC)


 * The ISA (Instruction Set Architecture) is designed by ARM - that's the ARMv8 64 bit architecture. The implementation, the pipeline how many of each functional unit they have what the branch target cache etc are like, is pretty definitely designed by Apple rather than being a Cortex A53 or A57 from ARM. Why on earth would Apple do otherwise? They recruited a whole bunch of CPU designers who worked on the DEC Alpha and in Intel who've already produced Swift and the ISA has been around long enough. As to signing licences Apple are famous for their secrecy and they've been associated with ARM since the year dot, they didn't acknowledge an ARMv7 architecture licence till after they released the A6.


 * By the way it is quite easy for a hardware design to be very similar even if the ISA is quite different. The 64 bit ARM Cortex A57 and A53 cores are very similar to their 32 bit A15 and A7 ones. Dmcq (talk) 09:21, 19 September 2013 (UTC)
 * The most convincing thing that it is an Apple design is the speed. With a 1.3 GHz it was going at 40% faster than a 2.4 GHz ARM A15. ARM themselves only predict a 30% to 50% uplift at the same clock speed when going from A15 to A57 - never mind at half the clock speed! Dmcq (talk) 10:06, 19 September 2013 (UTC)


 * This is still just speculation, I'm not an expert that knows you are wrong. About similarity, the ISAs are quite different and I doubt only the decoder is just affected. You could be right and only the decoder is different and from ARM and the rest is from Swift, still I don't know and don't have any proof and timing differences (you would need non custom-ARM to compare to) or a "smoking gun" in compiler code generation suggesting different microarchitecture (distinct ARMv8s/Cyclone vs. regular ARMv8). If it is likely then I will be back down a little. Still secrecy would not apply by now? iPhone 5s/Apple A7 has been announced and I can't find any press release from ARM Holdings (that I think would be appropriate), on an architectural license or even just acknowledging A7 existance - strange. comp.arch (talk) 10:21, 19 September 2013 (UTC)


 * I wouldn't treat "no announcement" as an indication that Apple just licensed a Cortex-A50 core. Apple aren't exactly the most public company about what they do, and they may have explicitly asked ARM to keep it quiet even after the chip was announced. Guy Harris (talk) 18:57, 19 September 2013 (UTC)


 * Dmcq, Are you sure about A7 being 40% faster than a 2.4 GHz ARM A15? That sounds kind of implausible.  My recollection is that Anand reported Cyclone cores significantly outperforming a whole range of devices, but I don't recall it being compared to a 2.4 GHz ARM A15. —RP88 (talk) 10:27, 19 September 2013 (UTC)
 * No I was wrong. Looking at it looks like the 32 bit performance at 1.3Ghz is 10% faster than a 1.99Ghz A15 which works out at the same frequency at over 60% advantage in 32 bit - still too large for ARM's estimates. The Apple A7's 64 bit performance compared to the ARM A15 in 32 bit works out at well over 2 times at the same frequency. Dmcq (talk) 11:20, 19 September 2013 (UTC)
 * Thanks for checking, good to know I didn't overlook something. But yes, I agree, the known performance advantage of the A7 per MHz is much better than ARM claims for either the Cortex-A53 or Cortex-A57. This is strong evidence that the A7 is a custom Apple design, unless ARM has been shockingly humble in their claims for the A53/A57. —RP88 (talk) 11:41, 19 September 2013 (UTC)
 * If this is true, then it could be another microarchitecture or could it be just bigger cache than ARM used? If I new microarchitecture is really more probable then I don't object to taking dubious out. Or could we say "AnandTech says it is an Apple-designd microarchitecture", that could be true and maybe non-speculation(?) since he has benchmarks and seems to have researched more (not just some rumors). comp.arch (talk) 13:22, 19 September 2013 (UTC)
 * I had a look at the A57 performance predictions at and the 30%-50% would only be with a speed up from going to 20nm. The prediction is only about 20-30% increase at the same frequency for 32 bit workloads which is way below 60%. The range I was thinking of is also about right I believe changing to 64 bit. Dmcq (talk) 14:24, 19 September 2013 (UTC)
 * Note I already took "dubious" out, but your link says "general object oriented code is also expected to improve significantly when recompiled to AArch64". This seems to be an old (slightly wrong) graph. comp.arch (talk) 12:03, 23 September 2013 (UTC)
 * Perhaps addresses you points whatever they are. It is based on the same stuff but they had a talk with the people. Are you really still thinking the Apple could be using A57's? Dmcq (talk) 13:40, 23 September 2013 (UTC)

If I understand you correctly, you dispute the statement "Apple designed" with regards to the two cores in the A7. If they're not designed by Apple, they presumably must be either Cortex-A57's or A53's. So I guess you're saying that you think it is much more likely that Apple is using a dual-core Cortex A53 or A57. Correct? Obviously Anand disagrees, for that matter, the portion of quote that you've elided with [..] is "These aren’t Cortex A57 derivatives (still too early for that)". Do you have any references you can point to where an analyst contests the conclusions of Anand's review? Admittedly it's only been just over a day since his review went live, so it's still early, such articles may well be forthcoming. I personally think that there is no way that the A7 is using Cortex-A57 cores (wrong cache sizes) or Cortex-A53 cores (too slow per MHz given the known performance and 1.3 GHz clock), but this is definitely not an area in which I claim any special expertise. I have no objection to leaving the "dubious" template on the "Apple designed" claim for awhile to encourage other editors to speak up or to track down references that contest Anand's conclusion that the ARM cores in the A7 were designed by Apple. —RP88 (talk) 10:13, 19 September 2013 (UTC)
 * Not sure which one (or both?), but I would guess they use Cortex-A57. Regarding "Cortex-A57 cores (wrong cache sizes)". What is it's cache size or A53 anyway? You seem to know (note Apple doubled compared to ARMv7s Swift's). Not sure it's defined (the pages on them is still missing in Wikipedia btw..). Often the cache size for ARM's are choosable - don't think chosing some different size makes it a custom design - wouldn't that be stretching the "custom-designed"-definition if that would be the only difference from the ARM's ARMv8-cores? comp.arch (talk) 10:28, 19 September 2013 (UTC)
 * The A53 is the slow, power efficient processor twin to the A57 which is ARM's highest performance processor (they can be configured in an ARM big.LITTLE configuration with A57 as the "big" and A53 as the "little"). I could be wrong (it's been awhile since I heard ARM's presentation on the A50 series), but my recall is that the design of the A53 permits core licensees to choose from a 8-64KB for the L1 instruction & data caches and from 512KB-2MB for the L2 cache; however the A57 only supports a fixed 48KB instruction cache, fixed 32 KB data cache, but core licensees can choose 512 KB-2 MB for the L2 cache.  It looks like User:Imroy added that information to the List of ARM microprocessor cores article last year. Since the Cyclone is known to have 64 KB instruction cache and data cache, it's probably not a dual-core Cortex A57.  —RP88 (talk) 11:01, 19 September 2013 (UTC)
 * Well I cut down my estimate of the difference from the ARM A15 above but it still is way above ARM's estimates for how much faster the A57 would be over the A15. I suppose it is possible they improved the design since or the compilers have turned out far better than they used in their simulations but I think that's unlikely. I really can't see how there can be much doubt Apple designed it themselves so 'dubious' is simply unreasonable. That someone wants a better citation would II guess be fair enough. Dmcq (talk) 11:31, 19 September 2013 (UTC)
 * "the A57 only supports a fixed 48 KB instruction cache" if this is true, that is A57 does not allow 64 KB then is seems to be at least a tweeked A57 (still if that is only done to allow a bigger cache does that warrant "Apple-designed" - custom?). Since the A57 is faster then I guess it can only handle a smaller cache size in the same process node, maybe Apple has better process available and can then expand the cache size within ARM parameters? comp.arch (talk) 13:40, 19 September 2013 (UTC)
 * I really cannot understand why you are going on about this. Anandtech say Apple designed it. The performance indicates it is not an A57. Apple have the experience, time, and money and desire to produce it. So exactly why is the Anandtech statement dubious, i.e. why should we take notice of what you are saying compared to a reliable source? Dmcq (talk) 14:09, 19 September 2013 (UTC)

The point is that we/Wikipedia shouldn't speculate or evaluate Anand's article. They say that it's not an Apple ISA, Apple have stated that it's ARMv8, we have the references. So, there's no dispute over the ISA. The Article reflects that. Anand says this: "The CPU cores are, once again, a custom design by Apple." and that's that. It might be dubious in our educated minds, but it's backed up by a very reputable reference and our hesitation should not be reflected in the article. That'd be original research and probably some other violation of policy. Chipworks or some other source might shed some other light on this matter, but it's not our place to speculate, it's our place to write an article backed by the best references as possible, and if this is AnadnTech then that's that. For now. Until a better source… -- Henriok (talk) 11:50, 19 September 2013 (UTC)
 * Already took "dubious" out, we'll see. comp.arch (talk) 12:03, 23 September 2013 (UTC)
 * Exactly. Anandtech is reputable and says Apple designed it. We shouldn't say that is dubious without some good reason. And in fact I think from looking at the speed that it is practically certain it is not an ARM A57 and was designed by Apple themselves. So can we just remove the dubious? Dmcq (talk) 12:16, 19 September 2013 (UTC)

Series6 GPU
I think Anand's speculation about the 4-cluster configuration of the GPU is incorrect. Imagination Technologies has stated that the Series6 GPU is 20x faster than the Series5 GPU, and the makers of Infinity Blade III claim that the iPhone 5S graphics is 5x faster than the iPhone 5; thus, a single core configuration would be more consistent with those sources. I've removed the speculations about the GPU configuration. --Martin Kraus (talk) 08:30, 22 September 2013 (UTC)
 * In the chipworks picture of the chip[ (click on the red square under the A7 picture), it looks to me like the 2 units of the dual cpu form the bottom left rectangle and 4 units probably forming the GPU at the bottom right. I don't know what is in a cluster - is it composed of four units? Dmcq (talk) 11:46, 22 September 2013 (UTC)
 * Yes, Martin Kraus appears to be a bit confused about the PowerVR Series6 GPUs. HIs logic is based on a faulty premise, that the slowest member of the Series6 is 20x faster than the Series5XT part in the iPhone 5.  That isn't true.  The large performance multipliers reported by IMG were compared to early Series5 parts, not compared to the many-times faster SGX543MP3 in the iPhone 5... and that doesn't even take into consideration things like the extent to which Infinity Blade III fully exploits the new GPU, the effect of clock speed, etc.  Furthermore, unlike the PowerVR Series5XT family, all of the GPUs in the Series6 family (i.e. G6100, G6200, G6400, G6230, G6430, and G6630) are single-core GPUs.  Instead they differ in the number of "clusters" they contain. Each cluster is a multi-threaded processing unit optimized for common GPU compute tasks, called a "shader."  The IMG blog post "PowerVR G6630: go fast or go home" is a good basic introduction to this architecture. Looking at the AnandTech's annotated image of the A7 die, the blue rectangle encloses the GPU. With regards to the die image, I think I can see: (a) four shader clusters at the corners of the GPU, (b) the common core management, setup, and post-processing logic arranged vertically down the center of the GPU, and (c) two tiling units at the 3 o'clock and 9 o'clock positions. This lines up with the G6430 quite well.  Of course, that's all OR on my part. Additional reading:   —RP88 (talk) 14:53, 22 September 2013 (UTC)
 * The die image is convincing. --Martin Kraus (talk) 20:36, 22 September 2013 (UTC)
 * But then again, how do we know that all 4 clusters are actually used? --Martin Kraus (talk) 19:35, 23 September 2013 (UTC)
 * Removing a sourced statement, and replacing it with nothing, based on further speculation and original research without a linked source? I'm putting AnandTech's back in, until better sources comes along. -- Henriok (talk) 13:03, 22 September 2013 (UTC)
 * I agree with your decision. Ultimately we have to use the values reported by sources. AnandTech is a high profile site with a reputation for accuracy, if AnandTech is truly reporting bogus information in their review of the iPhone 5S and A7 it won't be long before they either post a correction or a reliable source disputes AnandTech's findings. —RP88 (talk) 14:53, 22 September 2013 (UTC)
 * Just a comment: Anand's "sourced statement" reads: "Based on the delivered performance, as well as some other products coming down the pipeline I believe Apple’s A7 features a variant of the PowerVR G6430." I.e. Anand makes it explicit that this statement is a speculation. --Martin Kraus (talk) 20:36, 22 September 2013 (UTC)
 * I agree with that so I've changed the article to explicitly say it is a belief from Anandtech. Dmcq (talk) 21:54, 23 September 2013 (UTC)

Why should we assume an "S5L8960X" is an SoC?
The reference cited for the A7 being an "S5L8960X" bases that on an item in a plist for a device driver; the driver is for an I/O device (the keys in the plist are for an I/O Kit device), the IONameMatch key has a value of "displayport,s5l8960x", the driver also has a "PixelClockLimit" key, and a Google search for


 * "dptx" "display port"

suggests that a "DPTX" or a "DPTx" is something related to DisplayPort. Might "TX" stand for "transmitter"?

Looking for


 * s5l8950x "display port"

found a MacRumors post in which a user "GnillGnoll" comments:


 * I'm surprised no one seems to have picked up on the actual contents of that screenshot yet. Formatting out the SGML tags:
 * AppleSamsungDPTXControllerS5L8950X
 * IOClass - AppleSamsungDPTXControllerS5L8950X
 * IOProviderClass - AppleARMIODevice
 * IONameMatch - displayport,s5l8950x
 * PixelClockLimit - 155,000,000 (= 0x93d1cc0)
 * AppleSamsungDPTXControllerS5L8945X
 * IOClass - AppleSamsungDPTXControllerS5L8945X
 * IOProviderClass - AppleARMIODevice
 * IONameMatch - edp,s5l8945x
 * DPTX probably stands for DisplayPort Transmitter. eDP likely is Embedded DisplayPort, a standard for transmitting video signals to a built-in screen, while DisplayPort is a standard for external video signalling.
 * A pixel clock of 155 MHz is sufficient for 1920x1080 at 60 Hz, probably even 1920x1200. Unfortunately the screenshot does not have the pixel clock limit for the eDP interface, nor any indication whether there may be additional interfaces.
 * IONameMatch - edp,s5l8945x
 * DPTX probably stands for DisplayPort Transmitter. eDP likely is Embedded DisplayPort, a standard for transmitting video signals to a built-in screen, while DisplayPort is a standard for external video signalling.
 * A pixel clock of 155 MHz is sufficient for 1920x1080 at 60 Hz, probably even 1920x1200. Unfortunately the screenshot does not have the pixel clock limit for the eDP interface, nor any indication whether there may be additional interfaces.
 * A pixel clock of 155 MHz is sufficient for 1920x1080 at 60 Hz, probably even 1920x1200. Unfortunately the screenshot does not have the pixel clock limit for the eDP interface, nor any indication whether there may be additional interfaces.

so perhaps the earlier "S5L8950X" and "S5L8955X", along with the "S5L8960X", are DisplayPort controllers, not entire SoCs. Guy Harris (talk) 20:04, 17 November 2013 (UTC)


 * In addition, further searching found another MacRumors post, in which user "glassman" says:


 * Looks like Apple integrated Samsung's DisplayPort transmitter IP block. Logical given the chip is manufactured by Samsung on their process and this IP is in their process proven library - there is no point in reinventing the wheel or going elsewhere for said IP.
 * Lightning connector has two generic differential data pairs that can be assigned to any particular use. So far one of them has been used for USB D+/D-, but it's easy to imagine the other one used for a single lane DisplayPort output. Remember the iPhone In-Dash integration where it would drive the car's built-in screen? Make sense, right?
 * All Apple A series SoC part numbers actually follow Samsung's processor/SoC part numbering scheme - all this S5Lxxxx is a continuation of Samsungs's off-the-shelf SoCs used in iPhone 3GS and prior. I wonder when Apple designs a chip to be made at TSMC, will they change the part number to something unique?
 * http://www.samsung.com/global/business/semiconductor/file/product/Mobile_SoC-0.pdf
 * All Apple A series SoC part numbers actually follow Samsung's processor/SoC part numbering scheme - all this S5Lxxxx is a continuation of Samsungs's off-the-shelf SoCs used in iPhone 3GS and prior. I wonder when Apple designs a chip to be made at TSMC, will they change the part number to something unique?
 * http://www.samsung.com/global/business/semiconductor/file/product/Mobile_SoC-0.pdf
 * http://www.samsung.com/global/business/semiconductor/file/product/Mobile_SoC-0.pdf


 * The document he cites at the end says, in the "MOS Code Information" section starting on page 7, that an identifier starting with "S5" is an "MOS", as opposed to a "Microcontroller" or "MSP". The "L" indicates that it's "Optical"; I'm not sure what "optical" means there - DisplayPort may drive a device that sends light to your eyeballs, but the signal itself is electronic, not optical.  I don't know whether that document applies to the name "S5L89xx" or not. Guy Harris (talk) 20:18, 17 November 2013 (UTC)


 * I assume you meant S5L8960X? you edited your comment You make a good point, that reference isn't great.  However, we know that S5L8960X is the APL0698 due to Samsung naming conventions going back at least as far as the APL0278 / S5L8720, but that extrapolation probably counts as WP:OR. I've added an AnandTech reference that explicitly says "Apple's S5L8960X SoC (otherwise known as Apple's A7)." —RP88 (talk) 20:22, 17 November 2013 (UTC)


 * Hopefully the reference the AnandTech person found was something other than a plist for a DisplayPort driver.... Guy Harris (talk) 20:54, 17 November 2013 (UTC)

Are you suggesting that the APL0698 and S5L8960X isn't the same device (and the other similarly named devices with complementary backwards naming scheme)? The APL0698 probably is a Display Port Controller, among a very large amount of other things, since it is a SoC, that's one of the functions that is included in the chip. The plist regarding the eDP controller isn't the only place where this designation (and similar designations) is found. It's assumed everywhere that APL0698 and S5L8960X is the same device, and breaking them apart would be original research since no one (as far as I've seen) besides Guy have suggested otherwise. So I must demand a source for doubting that these are two different devices. Unless it's provided we should just assume that it is, since everyone think it is. -- Henriok (talk) 22:17, 17 November 2013 (UTC)


 * I'm saying that one plist isn't conclusive. If the designation is found elsewhere, referring to other components of the SoC, those should be given as references, so that it's clearer that the designation refers to the entire SoC.


 * The SoCs with ARM-designed application processor cores could be relatively straightforward Samsung products (I assume that, as they're SoCs, products such as the S3C6400 that iFixit speculated could be the processor in the original iPhone, but I doubt that the A6/A6X/A7 correspond so neatly to a particular Samsung SoC design that they sell (removing the application processor core design and replacing it with your own is a bit of a bigger change than adding your own blocks to an existing SoC). Perhaps either they or Apple use S5L designators for the SoCs they fab for Apple, as opposed to the Exynos SoCs they sell in the general market. Guy Harris (talk) 00:27, 18 November 2013 (UTC)

APLzyx before S5Lxyz
I would like to suggest that we change all "product codes" in the infoboxes to what's printed on the package, instead of what they might be called in software. What's printed on the package is what's visible for an examiner. What it might be called in software could be anything and wouldn't be very obvious for a person looking at a device. I.e. APL0698 is the primary name we should use, instead of S5L8960. -- Henriok (talk) 22:30, 17 November 2013 (UTC)
 * Examining the existing uses of these two terminologies on the web it looks like silicon-industry news sites like EETimes and reverse engineering companies like Chipworks or UBM Techinsights prefer the APLxxx terminology. It's really only the jail-breaking community that seems to prefer the S5L terminology.  I'd support that change, the S5L codes do appear to be more obscure.  I'd also suggest changing subsection subtitles on Apple A5 to use the APLxxx codes as well. It looks like this issue came up before at Talk:Apple (system on chip) and it was decided to prefer the use of the APL terminology. —RP88 (talk) 12:06, 19 November 2013 (UTC)

Unclear what ARM's role is
First para says "While not the first 64-bit ARM CPU". But ARM's role not clarified in article text.  Tu rk ey ph an t 11:45, 28 January 2014 (UTC)
 * ARM's role is defined in respect to the scope of the article, in the sense that this CPU is using the ARM instruction set, and if you'd like to know more about ARM, it's liked to that article. -- Henriok (talk) 16:11, 28 January 2014 (UTC)

Patent issues October 14th
The patent has nothing to do with branch prediction but value prediction (which is a completely different topic although both are predictors). Please read the patent for more information. — Preceding unsigned comment added by 146.198.153.77 (talk) 21:37, 15 October 2015 (UTC)

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 * It moved; it didn't disappear. Fixed. Guy Harris (talk) 18:27, 9 July 2017 (UTC)

Not first 64-bit ARM?
The article's opening states "While not the first 64-bit ARM CPU", but when I went to the linked citation it didn't support that claim, but instead discusses an FPGA simulation of a 64-bit chip. The citation states "The demonstration ... provides pre-silicon customer evaluation of our 64-bit ARM solution and paves the way for a more sustainable future of cloud computing as we leverage this architecture to provide high-performance devices that consume less power and lower costs compared to today’s server chips."

Is there a better citation available? Some Googling seems to indicate that Apple's was the first volume (non "lab demo") 64-bit ARM chip in use, but if someone has a good citation either way, it would certainly help. 2A02:AA13:7200:2400:B0E4:4260:454F:EA5A (talk) 13:03, 7 September 2018 (UTC)