Talk:Binary multiplier

Misc
The 4 bit by 4 bit multiplier figure looks flawed - namely, the ordering of the bits of Multiplicand B is reversed when they enter 2nd and 3rd adders.

Fixed. Quart$parcial prouductst$ (talk) 20:47, 17 March 2010 (UTC)
 * The fixed version is a 4 bit multiplier, it was reverted for the time being. Once it is reverted I suggest we do an article rewrite because it doesn't really match the style of other pages, and its kind of hard to read.Deadcellplus (talk) 20:26, 13 October 2008 (UTC)

Multiply Instruction Bit Sizes

 * Note: ARM Cortex-A53/A57 (ARMv8-A) requires an extra instruction to create the 128-bit result.

I'm considering adding this table to the first section. It still needs further expansion. Thoughts? • Sbmeirow  •  Talk  • 01:21, 28 January 2015 (UTC)

Refs, x
Please change all instances of the letter x used as a multiplication sign to ×.|Please markup the link in the first section as a ref. — Preceding unsigned comment added by 109.70.40.55 (talk)
 * Semi-protection-unlocked.svg Not done: According to the page's protection level you should be able to edit the page yourself. If you seem to be unable to, please reopen the request with further details. &#8209;&#8209; El Hef  ( Meep? ) 20:27, 9 April 2022 (UTC)

Redundant gate in 2×2 bit multiplier schematic
The AND in the second column generates (A0∧B1)∧(A1∧B0): the AND of all four inputs, the only way to get a product of 8 or higher, perfect for C3. Anding in any other AND of inputs, including the A1∧B1 shown, changes nothing. 188.109.124.100 (talk) 16:45, 29 July 2023 (UTC)


 * Not just that, the bottom-most AND gate (generating A1^B1) is also unneeded. The XOR generating C2 can be done as (A0∧B1)⊕(A1∧B0). D0SBoots (talk) 10:16, 18 November 2023 (UTC)