Talk:Duron

Changed made by User:Swaaye
I removed several of the recently added Infos. --Denniss 23:47, 9 January 2006 (UTC)
 * 1) The last Duron is called Applebred and not Appalbred (I have two, one A- and one B-model, every CPU-ID program tells me Applebred).
 * 2) Appaloosa was cancelled
 * 3) Both Slot-A and Socket-A Athlons/Durons had Exclusive L2-Cache, Core was not very different
 * 4) P3-Celeron was available with 100 MHz FSB, too. I'm not sure with inclusive L2-Cache though
 * 5) Lots of stuff about Caches do not belong to this article, use CPU cache for this kind of stuff

Hi Denniss, I'm not sure why we are having such conflict on these issues. Please check my references.


 * 1) The last Duron is called Applebred and not Appalbred (I have two, one A- and one B-model, every CPU-ID program tells me Applebred).
 * This is partially true. It is called both, please research this on Google. Or look at my references.


 * 1) Appaloosa was cancelled
 * Yes, please check my references. Note the "Appal" in the name though.


 * 1) Both Slot-A and Socket-A Athlons/Durons had Exclusive L2-Cache, Core was not very different
 * Check Sandpile.org. Athlon Slot is Inclusive. http://www.sandpile.org/impl/k7.htm. Cache design was vastly different.


 * 1) P3-Celeron was available with 100 MHz FSB, too. I'm not sure with inclusive L2-Cache though
 * Most Definitely Not. Please research. P3-Celeron was crippled by its small cache and 66MHz bus for most of its life. Not until Celeron 800 in 2001 did Intel finally up the bus speed. Duron was out for half a year before Intel did this. AND, Intel CPUs have always had inclusive cache designs. It is not a flaw, just a different way to do it. In fact, it is part of the reason for the high performance of their chips. But in a low-cache CPU it is not an advantage. Celeron's cache also had half the associativity of Pentium 3's.


 * 1) Lots of stuff about Caches do not belong to this article, use CPU cache for this kind of stuff
 * This may be true, but it is also what made the Duron perform so well as a value CPU. It kept a lot of performance even with a limited L2 cache. I think that is important.

I will be re-adding this information again. I would like to discuss this with you, and to have you please read the references I spent time finding to prove this information as accurate. --Swaaye 00:06, 10 January 2006 (UTC)

You know, if you're so inclined to rip out my referenced facts, you could at least do it and not cause redundancy too. Please read my references and comment on them before wiping out hours of my work. --Swaaye 01:14, 10 January 2006 (UTC)


 * Your should check your "facts", the Appaloosa was planned but cancelled, the Applebred is just a variant of the T-Bred with partially disabled L2-Cache and nothing more. It seems sandpile.org has some problem with inclusive and exclusive L2-Cache, see P4 with exclusive L2-Cache but inclusive L3 ?!? A quote from one "Google source": Wir Moderatoren haben vorgestern mit Jan Gütter gesprochen, er hat die Bezeichnung "Applebred" bestätigt, das reicht mir und ist für mich eine offizielle Aussage (short translation: Moderators have asked Jan Gütter (of AMD) and he confirmed Applebred, that's enough for me and is as good s an official statement) from here --Denniss 01:41, 10 January 2006 (UTC)

Denniss, Thank you for responding to me. That Sandpile is wrong about P4 is definitely concerning, and brings into question their credibility overall. I will look deeper into this Athlon-being-inclusive point. Really though I draw most of my perspective on performance between exclusive and inclusive from performance differences between the Celerons and their more endowed Pentium relatives. Also, thanks for finding that part about Applebred/Appalbred. I would never have checked a German forum! It is the strangest thing though, that the codename could be so confusing. The thing that helped me most remember Applebred was not the cache tweak, but it's name and how everyone spelled it out differently. So, it's probably worth mentioning both just due to that confusion. Of the Durons, I've only personally owned Spitfire, but have had every revision of Athlon after the Slot.

And yeah I know Appaloosa was canceled. I saw that on several sites. Geek.Com said he'd actually seen a few of them in systems though, but that it had not been officially announced/released. I wonder if that was because it was based on Thoroughbred A, and that chip was a poor clocker to say the least. So they canned it and went to Thoroughbred B/Appalbred...

--Swaaye 05:04, 10 January 2006 (UTC)
 * Applebred are both available as T-Bred A and T-Bred B, I have a 1600er A and a 1400er B (as Athlon XP now). I have not much Info about Appaloosa but it's possible it was planned as a CPU with physically only 64 KB L2 available analog to Spitfire and Morgan. --Denniss 05:44, 10 January 2006 (UTC)

No SSE
Hi,

I think there is a small "bug" in the article. I have access to a Duron which does not have SSE, but the article lists them all with SSE. Here is the /proc/cpuinfo output from Linux, if it helps:

20:52 athlon:~ # cat /proc/cpuinfo processor      : 0 vendor_id      : AuthenticAMD cpu family     : 6 model          : 4 model name     : AMD Athlon(tm) processor stepping       : 2 cpu MHz        : 900.037 cache size     : 256 KB fdiv_bug        : no hlt_bug         : no f00f_bug        : no coma_bug        : no fpu             : yes fpu_exception  : yes cpuid level    : 1 wp             : yes flags          : fpu vme de pse tsc msr pae mce cx8 sep mtrr pge mca cmov pat pse36 mmx fxsr syscall mmxext 3dnowext 3dnow bogomips       : 1802.69

(The SSE flag would normally appear after "fxsr" on an SSE-capable CPU.)


 * Spitfire has only a partial SSE implementation. It has the integer portion of SSE, but AMD calls it Extended 3DNow (which has other stuff too). So they can't say it's fully SSE compliant. --Swaaye 20:16, 4 June 2006 (UTC)

Die-locking
Applebreds were released (according to this page, I'm assuming it's correct) on August 21 2003, which translates to mid week 34 2003. The first die-locked chips (not necessarily Applebreds) began appearing in week 34, though it was rare to get a die-locked week 34-38 CPU. Week 39 was when die-locking became nearly universal, giving a period of about 4 weeks. The main thing is that the week number on the chips is not when the chip is bought - typical channel times back then were in the order of 2-4 weeks. On the other hand, the August 21 date probably isn't a "widely available for sale" date, which will cut a week or two off the other end. Hence where I get the ~4 week number. I'll see if I can dig up something more accurate, but given the rate of change in the tech world it may be hard to get. Until then, the ~4 week number (IMO) is a good start. 150.203.19.142 06:50, 8 February 2007 (UTC)

Just noticed that you may have been removed it because of it referring as well to the locking of L2 cache size. In the die-locked chips, BOTH the L3 (startup multiplier) and L2 (L2 cache size) bridges no longer have any effect. ie: any "multiplier-locked" chip is also "L2-cache-size" locked. The main reason this is not as widely mentintioned is that most people did not try and re-enable the extra cache. 150.203.19.142 07:01, 8 February 2007 (UTC)

Possible inaccuracies?
I recently took apart an old computer of mine to find that it had an AMD Duron processor in it. The date on the processor said 1999. The motherboard supported cpu clock speeds of 100mhz to 133mhz, so it's safe to assume the processor was limited to run within this range. The article claims the Duron processor was created in 2000, but I have one that is marked with the date 1999. 24.115.3.224 19:22, 1 March 2007 (UTC)


 * Look a the image of the Duron we have here, it is also listed with copyright 1999. But this date usually means the design is of 1999 but not the CPU itself. The time stamp looks like it specifies week 32, 2000, as date of creation for this core. Also the article does not claim it was created in 2000 but it was officially published at this date.--Denniss 22:29, 1 March 2007 (UTC)

Inconsistency in dates?
Article: "The Duron was discontinued in 2004..." Infobox: "Produced: 	From mid 2000 to 2006"

Which is right? 86.132.138.84 19:39, 13 November 2007 (UTC)
 * probably development was discont. in 2004 but it remained available until 2006 —Preceding unsigned comment added by 65.31.222.144 (talk) 22:10, 19 January 2009 (UTC)

Initial Duron vs First Socket A Athlon
When the Duron was first introduced, both the Duron and the Athlon ran fixed multipliers based on a 100MHz FSB (200DDR FSB) and were designed to do so, if only because there were no motherboards for them that supported a 133MHz FSB. For example, the VIA KT-133 chipset motherboards ran the CPU (Athlon and Duron) at 100MHz FSB (200DDR FSB) and could feed the SDR memory bus at its slower, asynchronous 133MHz (hence the KT133 designation) at a very high throughput for the time. AMD's own Socket A motherboard chipset at this time didn't even support async 133MHz SDR Memory let alone a 133MHz FSB.

Later motherboards with chipsets such as the VIA KT-133A, were introduced to support the "new" Athlons running at 1GHz+ with a 133MHz FSB. However, even then, there were "Thunderbird" Athlons sold at 1GHz - 1.4GHz produced for the older boards that ran at 100MHz FSB.

It wasn't really until the Athlon XP and the Morgan based Durons, that AMD would make a clear marketed deliniation between the FSB speed of the processors. — Preceding unsigned comment added by 24.10.146.29 (talk) 05:02, 6 March 2013 (UTC)

Right, well I changed it.

External links modified
Hello fellow Wikipedians,

I have just modified one external link on Duron. Please take a moment to review my edit. If you have any questions, or need the bot to ignore the links, or the page altogether, please visit this simple FaQ for additional information. I made the following changes:
 * Added archive https://web.archive.org/web/19991013102053/http://sandpile.org/impl/k7.htm to http://www.sandpile.org/impl/k7.htm

When you have finished reviewing my changes, you may follow the instructions on the template below to fix any issues with the URLs.

Cheers.— InternetArchiveBot  (Report bug) 00:32, 15 September 2017 (UTC)