Talk:Haswell (microarchitecture)/Archive 1

Release
Removed uncited line that stated a possible one year transition from Sandy Bridge. Likely an error due to Intel's adjusting the Sandy Bridge timeline to ensure the Nehalem is on the market for long enough. Originally Sandy Bridge was supposed to launch in 2010 with Haswell following in 2012. If Sandy Bridge has been pushed back into 2011 then it is likely that Haswell has been pushed back into 2013. Logically Intel would not increase the length of the Nehalem architecture's lifetime in order to maximise their profits in developing it and then turn round and shorten the period of time that Sandy Bridge would be on sale, thereby decreasing their return on investment on that particular architecture. Cyclonius (talk) 11:02, 6 January 2010 (UTC)

Rockwell to Boradwell - real or hoax?
According to various sources, Rockwell has renamed to Broadwell. However, the information seems to have originated from SemiAccurate, which is labeled as a "satire" site. In addition, the article was posted on April Fools' Day, which makes it seem even more suspicious.

So is there any truth to this? Should we revert it back to Rockwell for now? --Ixfd64 (talk) 01:42, 27 April 2011 (UTC)


 * So, let's revert it back to Rockwell then? Can't seem to find a reliable source to keep Broadwell... --Vittau (talk) 01:25, 10 May 2011 (UTC)


 * This is further confused by the appearance of "Rockwell" as the successor to Haswell in this newly leaked roadmap: http://www.xbitlabs.com/news/cpu/display/20110726174039_Intel_Readies_Skylake_Micro_Architecture_Post_Haswell_Era_Begins_to_Shape.html


 * The authenticity of this roadmap has not been verified however. 83.226.206.82 (talk) 11:36, 29 July 2011 (UTC)

Haswell New Instruction Descriptions Now Available
Everything you want to know about Haswell is now available from Intel: http://software.intel.com/en-us/blogs/2011/06/13/haswell-new-instruction-descriptions-now-available/

Sorry, I'm not tech/wiki enough to read, decipher and edit the article. — Preceding unsigned comment added by 76.76.134.10 (talk) 21:18, 16 June 2011 (UTC)

Making changes
I noticed that changes are not sourced, and a search on google does not show anything about the information provided in the change. (Not the first time that this has happened) Please do source your change where possible. thanks! Xxxxxls2 (talk) 10:09, 23 June 2011 (UTC)

Ivy Bridge?
Is this Ivy Bridge? Or is this the successor to Ivy Bridge? 98.114.237.231 (talk) 19:25, 13 September 2011 (UTC)

Strictly speaking, it is the successor to Sandy Bridge as mentioned in the article. Because Ivy Bridge is basically a die shrink of Sandy Bridge, so there is no change in architecture. 175.156.212.145 (talk) 12:52, 16 September 2011 (UTC)

Haswell Cache
I accidentally pressed enter halfway during the edit. What i meant was, a search on the internet did not come up anything about haswell's caches, if there is indeed a source present, please add it in. ty! 175.156.220.188 (talk) 10:05, 26 September 2011 (UTC)

"General Purpose Register [...] will be doubled [...]"
I removed this from the article


 * General Purpose Register (GPRs) and Floating Point Register(FPRs) will be doubled from previous generation.

Can somebody explain to me what "General Purpose Register [...] will be doubled [...]" even means? Specifically the word "doubled" - what will be doubled? Thue | talk 18:59, 16 March 2012 (UTC)

"Why do people change cache size data?"
There have been edits back and forth on whether the caches are 32 kB L1 data + 32 kB L1 instructions, 256 kB L2 cache (these per core) carried over from Ivy Bridge (which are in fact the Ivy Bridge sizes, and which are the sizes visible in the references given), and 64 kB + 64 kB / 1 MB caches, in contradiction with the given reference, and not the same as Ivy Bridge, even though this is implied. Now the latest edits to 64/64 have figured, well, let's even remove the references and just postulate it and without further ado. My question: why? Do you have a good reference for 64/64? If so, would you be willing to share it? Otherwise, the right thing to do is to put the reference and the consistent 32/32 numbers back. — Preceding unsigned comment added by 89.150.76.46 (talk) 07:09, 6 June 2012 (UTC)

"Up to 2~4 cores available in consumer market"
Really? This seems unlikely given that the newest Sandy Bridge-E processor has 6 cores and one with 8 is forthcoming (either SB or Ivy Bridge). I highly doubt they'll go backwards and limit it to 2 or even 4 cores. Why does this article feature speculation anyways, even if it's sourced? Telanis (talk) 02:26, 19 November 2011 (UTC)

The die shot comparing Haswell to ivy bridge and sandy bridge would seem to confirm up to 4 cores in the consumer market (i.e. not the LGA 2011 server platform, but more of the 2 channel 13XX socket):  http://www.google.com/imgres?um=1&hl=en&sa=N&biw=1024&bih=734&tbm=isch&tbnid=Tn7KYK7eQEBrgM:&imgrefurl=http://www.overclock.net/t/1205858/obr-haswell-die-size-revealed&docid=hpGeD78_qGwOzM&imgurl=http://cdn.overclock.net/2/29/29f21d20_cpus.png&w=1600&h=461&ei=RbgyT5uHKsGctwekqqSgBw&zoom=1&iact=rc&dur=161&sig=105423793670273668978&page=1&tbnh=51&tbnw=176&start=0&ndsp=20&ved=1t:429,r:1,s:0&tx=101&ty=40 According to this, the haswell die is ~ 10-15% larger than Ivy Bridge.. but will feature a larger GPU.. most likely confirming 4 cores as upper limit unless intel really shrunk down the core size on the same process as ivy bridge.. — Preceding unsigned comment added by 192.91.147.34 (talk) 18:02, 8 February 2012 (UTC)

Perhaps the info isn't final. Conceivably there still could be a 6-core among the mainstream performance (read: i7) platforms. Also consider that the biggest iGPU, GT3, is reserved for the mobile/ultrabook segment.--Azul120 (talk) 22:56, 18 February 2012 (UTC)

AMD will be coming with 16/32 core chips in the future, so these specs aren't final. Markthemac (talk) 05:52, 20 April 2012 (UTC)

It looks like the mobile Haswell chips might have quad-core versions after all. It's likely that the claim about them having only two cores was referring to ultrabooks. --Ixfd64 (talk) 16:05, 10 July 2012 (UTC)

Conflicting data?
The article says that Intel have used a 14 stage pipeline since the Core architecture, however this article says that Nehalem/Westmere and Sandy Bridge/Ivy Bridge are in the 16-19 range; which makes sense considering how high the overclocks on SB and IB (Or even Nehalem compared to Core 2 Duo, all things considered) are, Anand didn't provide a source but considering there's conflicting evidence, should the "(since the Core microarchitecture)" part be removed? Democrab (talk) 18:42, 20 July 2012 (UTC)

The pipeline is 14 stages if there is a hit in the micro op cache, 19 if it misses.

"$50 - $70 graphics cards"
Is there a way we can rephrase this so it will mean something to someone reading it in 5 years time? "...bringing its performance on par with the $50 - $70 graphics cards" —Pengo 07:48, 9 September 2012 (UTC)

not to mention current ivy bridge hd 4000 performs very much better than a "$50 - $70" card - I was shocked by how powerful it is... — Preceding unsigned comment added by 86.28.239.248 (talk) 11:51, 8 October 2012 (UTC)

Reliable?
Is this reliable? It doesn't point out its own sources.--Jasper Deng (talk) 04:48, 14 June 2012 (UTC)

Nope. — by Echrei (talk • contribs) 22:23, 7 August 2012 (UTC)

It mentions that the PCH "may be" reduced to 32nm from 65nm. I understood it was supposed to be on 22nm as a preparation for going full SOC with Broadwell / 14nm, since making all the components with the same process tech is usually the precursor to SOC. 66.68.18.249 (talk) 05:48, 18 December 2012 (UTC)

How to distinguish various GPUs on the processor tables.
I think we should remove the following text, and practice going forward: "Processors featuring Intel's HD 5000 (GT3) graphics are set in bold and will be released in Q3 2013. Other models will feature HD 4600 graphics [40]"

Mostly because, there is no longer a simple either, or arrangement for Intel's iGPUs. Desktop processors will feature either GT1, or GT2 graphics. Mobile processors will have the options of GT2, GT3 and GT3e. Also, it looks like there will be additional differentiation within given hardware(GT2, GT3, or GT3e) based on the TDP of the particular SKU.

I added the GPU column to the mobile table for this reason. I think a section explaining exactly what each GPU model number means, with regards to hardware and clock speed, is advisable once we have the necessary data. 67.190.6.143 (talk) 16:22, 7 February 2013 (UTC)

Is the 'List of Haswell processors' reliable?
The tables of upcoming processors seems unreliable, a lot of the information is sourced, and the models are linked to the previous generation Ivy Bridge models. It looks like it was filled in based on the previous models with a bit of estimation. I can't find anywhere that the models or many of the specifications are listed, officially. — Preceding unsigned comment added by 82.45.11.18 (talk) 21:32, 11 February 2013 (UTC)

The tables reflect the best information available. There are currently no official specifications publically available. The information on the tables comes from two documents believed leaked by one or more of Intel's OEM partners. These leaks are expected, and have historically been accurate.67.190.6.143 (talk) 22:37, 11 February 2013 (UTC)

No the links all all wrong
No the links all all wrong — Preceding unsigned comment added by 41.177.19.134 (talk) 12:17, 13 February 2013 (UTC)

I see what you mean. I had only ever clicked on the few that link to an error page. I assume this was done to make it easier to fill in the correct addresses once the new pages are live, rather than having to put in all new links. Easy enough to make sure none incorectly link to actual product pages.67.190.6.143 (talk) 06:12, 14 February 2013 (UTC)

How is the 450$ pricing backed up?
There is a the line with the 450$ price (on tray) for the 4770K model. Not only that Intel normally has comparable prices in each generation (see 3770K and 2700K at 332$), making a release price of 332$ for 4770K likely; additioanlly I wasn't able to find any link about this specific information. Either put viable information in this section or delete everything not officially confirmed. — Preceding unsigned comment added by 134.102.26.49 (talk) 09:26, 21 March 2013 (UTC)

S0ix
Which processors support S0ix? All or just mobile ones? — Preceding unsigned comment added by 91.186.149.197 (talk) 22:54, 24 March 2013 (UTC)


 * Unclear at this time. Most likely mobile only, possibly U & Y series only.67.190.6.143 (talk) 09:49, 12 April 2013 (UTC)

Wrong Release Dates?
I don't think that the Haswell R models are going to be released at the same time of the rest of the i7 and i5's (just a hunch). The citation used for the release dates of the desktop i7's and i5's says that it doesn't really know what is going to be release that day, just that some are. Anyone found any better information? Thesagemarmot (talk) 23:17, 10 May 2013 (UTC)

release date redux
I updated the release date in the lede to June 1st, but this was reverted back to June 4th. Am I misinterpeting the sources, or should it actually be June 1st? Martijn Hoekstra (talk) 10:40, 3 June 2013 (UTC)
 * The official release date is 4 June, the releases on the 1st are just Intel softening up the ground so that their partners can talk about upcoming products.2601:1:9C80:82:D5F6:571C:57CC:BB49 (talk) 19:53, 3 June 2013 (UTC)

Retail vs OEM
Is it possible to add a column to the comparison table describing processors as either retail or OEM only? It would be useful for us amateur system builders, who would like to know which processors can actually be bought as single units from normal retailers. — Preceding unsigned comment added by 105.224.27.187 (talk) 11:57, 4 June 2013 (UTC)
 * I'm pretty sure that one is supposed to label a CPU as OEM only by stating this in the "Release Price" column. -XJDHDR (talk) 16:27, 4 June 2013 (UTC)

Access times for L1/L2/L3 caches
It would be useful to list the access times for the L1/L2/L3 caches, perhaps as part of the summary box at the top of the page. — Preceding unsigned comment added by 50.151.236.90 (talk) 17:36, 9 June 2013 (UTC)

Hyperthreading
Internal inconsistency on desktop processors / Hyperthreading. "All models support hyperthreading" yet "quad-core I5 do not support hyperthreading" My guess is hyperthreading is supported exactly when there are more threads than cores, but this is just a guess.Richpark (talk) 08:30, 7 July 2013 (UTC)

Low Performance Gains
Performance is actually pretty low over the last generation ranging from .03% to 8.8% in real world benchmarks. They average out at about 3% improvements in this review (if you take out all the synthetic benchmarks.) I suppose the real improvements is in better onboard video, and lower power consumption, but not in any real discernible way. Disappointing.

http://www.anandtech.com/show/7003/the-haswell-review-intel-core-i74770k-i54560k-tested/6

Darrellx (talk) 12:06, 14 June 2013 (UTC)
 * Feel free to make changes to the article, this is a wiki after all. Make sure you stick to the sources, make sure you give due weight to the sources, and remember not all processors have been released yet. Martijn Hoekstra (talk) 19:48, 18 June 2013 (UTC)

L4 cache... Really?
Why is the dedicated memory for on-die graphics card marked as L4 cache? As far as I can see, those 128 MB of on-package RAM in xxxxR CPUs are there to be used by the on-die GPU only. It can't be used by the CPU and act as a real L4 cache. Even ARK doesn't list xxxxR CPU's as having L4 cache. See the URL below for a discussion:

http://www.anandtech.com/show/6892/haswell-gt3e-pictured-coming-to-desktops-rsku-notebooks

-- Dsimic (talk) 21:26, 15 September 2013 (UTC)


 * Well, now I'm confused... Another article states that eDRAM / Crystal Well actually acts as a true L4 cache, and not just as on-package GPU memory.  Though, ARK says nothing about the existence of L4 cache.  Please see the URLs below...  Thoughts?


 * http://www.anandtech.com/show/6993/intel-iris-pro-5200-graphics-review-core-i74950hq-tested/3


 * http://ark.intel.com/products/codename/51802/Crystal-Well


 * http://ark.intel.com/products/76642/Intel-Core-i7-4770R-Processor-6M-Cache-up-to-3_90-GHz


 * -- Dsimic (talk) 11:42, 16 September 2013 (UTC)


 * In the end, it all points into the eDRAM being a true L4 cache, but the ARK still says nothing about it within the specs for cache sizes. -- Dsimic (talk) 18:20, 15 October 2013 (UTC)

Configurable TDP frequency figures
Are these confirmed anywhere? Can't find anything about them. --Azul120 (talk) 17:31, 15 October 2013 (UTC)


 * Well, cTDP seems to be around, like it is described in this forum thread, but there seems to be no info on cTDP and Haswell. Hm, a bit strange, if you agree? -- Dsimic (talk) 18:16, 15 October 2013 (UTC)


 * It is strange. I wonder if the deltas are applicable for all processors, or someone's just pulling them out of hot air. --Azul120 (talk) 21:42, 21 October 2013 (UTC)


 * Table 22 of the Haswell datasheet, vol. 1 lists the guaranteed frequency of all U and Y series SKUs running at cTDP down as 800MHz. I have no idea where the cTDP up frequencies came from, as I've never seen those values listed anywhere but here. 2601:1:9C80:82:C1BF:B5EF:84E0:8D31 (talk) 08:47, 17 December 2013 (UTC)


 * Sorry, cTDP up frequencies? I can see only those TDP values listed in this article.  Are those in fact turbo mode values? &mdash; Dsimic (talk) 14:43, 17 December 2013 (UTC)


 * The 4th sub column under Programmable TDP is "cTDP up". It works just like "cTDP down" only in the opposite direction, you spec better cooling and you can run the chip hotter. No, those are not Turbo Boost values. From the same Datasheet I mentioned earlier.
 * Nominal This is the processor's rated frequency and TDP.
 * TDP-Up When extra cooling is available, this mode specifies a higher TDP and higher guaranteed frequency versus the nominal mode.
 * TDP-Down When a cooler or quieter mode of operation is desired, this mode specifies a lower TDP and lower guaranteed frequency versus the nominal mode.


 * As I said I can't vouch for the frequencies listed, but the "W" values look correct.2601:1:9C80:82:C1BF:B5EF:84E0:8D31 (talk) 00:45, 21 December 2013 (UTC)


 * Thank you for a detailed explanation! I've edited the article so your descriptions are now included, please check it out.  By the way, is the datasheet you're referencing to publicly accessible?  If it is, that would be a great reference. &mdash; Dsimic (talk) 01:29, 21 December 2013 (UTC)


 * Regarding the Table 22 you've mentioned, is it in this PDF file, on page 67, titled Thermal Test Vehicle Thermal Profile for Processor (PCG 2013D)? There I see no frequencies you've referred to, and it's all about the relationship between CPU core temperatures and consumed power, in various C-states.  Any insights, please? &mdash; Dsimic (talk) 02:04, 21 December 2013 (UTC)


 * Almost, that's the desktop datasheet. You need the datasheet for U and Y series chips pages 63 & 64. Included.
 * I thought I had added that when I added the SDP column, but it's possible it was removed in a later edit. The datasheet for H & M series chips is under reference 61 on this article.2601:1:9C80:82:C1BF:B5EF:84E0:8D31 (talk) 05:46, 21 December 2013 (UTC)


 * Awesome, thank you very much! I've just edited the article, so much more info on SDP and cTDP is provided, and with quick quoted descriptions; please check it out. &mdash; Dsimic (talk) 23:47, 21 December 2013 (UTC)

Missing data in Mobile processor table
The base CPU clocks are missing in the Mobile processor data. Bobbozzo (talk) 03:42, 4 January 2014 (UTC)


 * Actually, they're listed under the "Programmable TDP" group of columns; "Nominal TDP" column; base frequencies for mobile CPUs are depending on the cTDP. &mdash; Dsimic (talk) 04:06, 4 January 2014 (UTC)

FIVR implemented as a separate 13x8 mm on-package die...?
I am not sure that this is actually the case. I checked out the referenced article, and it shows a presentation from Intel of an example FIVR, that IS implemented as a separate 13x8 mm on-package die, but that presentation doesn't seem to be talking about haswell specifically. While the article is in Chinese and I am reading it with google translate, it seems to only offer speculation as to what the final configuration in Haswell will be, not fact as to what it actually is. It even mentions that Haswell will probably not have a full 20 Cells, suggesting that 5 is more likely. Also, I have seen pictured of de-lidded Haswell CPU's and there is no second die on package. I am fairly certain that the FIVR in Haswell is indeed on die, using the same 22nm litho that the rest of the cpu is done in. Has anyone seen any additional information on this? Extide (talk) 22:59, 15 January 2014 (UTC)


 * Hello there! I've watched a few Haswell delidding videos on YouTube, and you're right.  Went ahread and [//en.wikipedia.org/w/index.php?title=Haswell_(microarchitecture)&diff=590919848&oldid=590915527 deleted] description of the FIVR being implemented as a separate 13x8 mm on-package die –  numerous Haswell deliding videos on YouTube clearly show there's no such separate die. &mdash; Dsimic (talk) 03:59, 16 January 2014 (UTC)


 * There is a separate, smaller die on some Haswell chips, it's the Iris Pro eDRAM rather than the FIVR so it was correct to remove it. James086 Talk  20:47, 22 March 2014 (UTC)

"Cannot easily pass 4.2ghz"
Hi, I run the largest Haswell overclocking guide on forums I have seen. We are bordering on 12,000 posts and I've charted 140+ overclocks with 4670k and 4770k. In the page it states that Haswell cannot easily pass 4.2ghz. As it happens, the lowest charted and noted overclock is 4.2ghz. To have a 4.2ghz overclock is technically to not be able to pass 4.2ghz. However, having a 4.2ghz puts you in the bottom 6 percentile according to my chart. Median OC is 4.5ghz. Therefore I find it inaccurate to say that Haswell cannot easily pass 4.2ghz as only the most unlucky people are stuck at 4.2ghz. Part of the issue is how Haswell overclocking is different than Ivy/Sandy, so many reviewers who had review samples very early on did not know how to overclock things properly. Here is the Google Doc containing the charting of all the overclocks I've seen thus far. https://docs.google.com/spreadsheet/ccc?key=0AjXDCk5eCp1gdEdENjlDYWl6ZnV4OVlNc0lMU1V3c1E&usp=sharing 108.223.242.103 (talk) 21:57, 27 March 2014 (UTC)Dark_wizzie


 * Hello there! In a few words, we need references for everything present within Wikipedia articles.  While your work is certainly correct, unfortunately it still can't be used as a reference based on Wikipedia's rules that disallow forums to be used as references, at least not alone.  Any chances, please, for providing other references, so we can change the article? &mdash; Dsimic (talk | contribs) 02:53, 30 March 2014 (UTC)

That is unfortunate because computer websites and magazines love to get their articles out as early as possible, and with a CPU that takes time to learn, pretty much always the early guides were inaccurate. (In fact, it took over a month to iron out misconceptions.) http://us.hardware.info/reviews/4855/9/workshop-how-to-overclock-haswell-processors-in-practice http://www.anandtech.com/show/7063/overclocking-haswell-on-asus-8series-motherboards-video The anandtech link shows JJ from Asus' video. In there he states that booting at 4.6ghz with 1.2v means you have a"pretty decent cpu". While I think JJ's figures are a bit optimistic, it is WAY above 4.2ghz. Look at HWbot's statistics on average OC: http://hwbot.org/hardware/processors#key=core_i7_4770k http://hwbot.org/hardware/processor/core_i5_4670k/

It's around 4.5-4.6ghz, which matches my chart. According to HWbot, it has collected approx 30,000 OC submissions for its data. I understand that Wikipedia has standards to prevent shoddy data on its pages, but any person who owns a Haswell chip that actually bothered to seek out help will know that "Haswells can barely pass 4.2ghz" is completely wrong. The original claim about 4.2ghz listed on Wikipedia features what looks like many sources but many of them are repeats of the same website, same article, just different page in the article. Plus, all of them but one were written June, before the CPU even came out. They have a sample size of one, we have the sample size of 140 here, 30,000 on HWbot.

One more, this is HardOCP listing info from JJ from Asus once again. The guy in the article clocks to 4.8ghz. Might be worth noting that JJ claims to have overclock boatloads of Haswell chips with the help of his team. (While I still feel JJ offers wrong if on multiple accounts, in this point I think he is correct.) 108.223.242.103 (talk) 03:35, 1 April 2014 (UTC)Dark_wizzie


 * You're right about sites and magazines racing to announce something they've barely put their hands on – in many cases. Anyway, the two references you've provided above are good enough for  to the article.  Please check it out. &mdash; Dsimic (talk | contribs) 05:18, 2 April 2014 (UTC)

Hello, thank you for the change, I appreciate it. 108.223.242.103 (talk) 23:23, 3 April 2014 (UTC)Dark_wizzie


 * You're welcome, and thank you for doing all the work and providing all these references. &mdash; Dsimic (talk | contribs) 02:19, 6 April 2014 (UTC)

The mobile section is outdated
It doesn't include this for example http://www.notebookcheck.net/Intel-Core-i7-4710HQ-Notebook-Processor.115084.0.html There could be others that have also been recently announced that are missing from this page. 2A00:C440:20:1094:981E:1E2E:F55D:D92E (talk) 16:48, 19 May 2014 (UTC)


 * Please, feel free to update the tables. That's how this place works. 2601:1:8D80:7BE:C4CE:B024:989C:4C82 (talk) 23:21, 29 May 2014 (UTC)

Haswell-E
I recommend removing the data for the Haswell-E processors, the clock speeds for the the 5960X don't make sense compared to existing products(8-core IVB, and the 4960X compared to other 6-core IVB Xeons). Also the original source for all the numbers is a forum post http://www.coolaler.com/showthread.php/315730-Core-i7-5960X%E3%80%815930K%E3%80%815820K-%E8%A9%B3%E7%B4%B0%E8%A6%8F%E6%A0%BC%E6%9B%9D%E5%85%89 .2601:1:8D80:7BE:C4CE:B024:989C:4C82 (talk) 23:21, 29 May 2014 (UTC)

predecessor / successor links
Wasn't there links to the previous and next version in the quick info box on the right at the top of these pages? I want to look between the versions quickly without going on a hunt for the right link.70.71.141.194 (talk) 20:27, 1 November 2014 (UTC)


 * That's available in the infobox, please have a look. &mdash; Dsimic (talk | contribs) 05:40, 4 November 2014 (UTC)

AGU?
In the "new features" section, what is an AGU? Bubba73 You talkin' to me? 07:45, 7 December 2014 (UTC)


 * Will be covered soon. &mdash; Dsimic (talk | contribs) 07:47, 7 December 2014 (UTC)


 * I'm guessing accelerated graphics unit or advanced graphics unit, but I don't know. Bubba73 You talkin' to me? 04:56, 8 December 2014 (UTC)


 * ✅, please . It's now covered by brand new Address generation unit article, which is pretty much a stub, but hey, that's still an article. :) &mdash; Dsimic (talk | contribs) 07:41, 8 December 2014 (UTC)

Table sorting
Hello, ! Regarding that removed sorting from one of the article's tables, the rationale is that no sorting is available for other tables in the article, or in similar tables in Sandy Bridge, Ivy Bridge (microarchitecture), and other similar articles. Thus, having the sorting available in only one table in only one of such articles is simply inconsistent, and—‌quite frankly—‌looks really ugly with a separate row containing only the sorting arrows. Also, the "instructions" are simply out of place. &mdash; Dsimic (talk | contribs) 13:34, 30 March 2015 (UTC)


 * You are obviously a newb concerning table sorting. It is on thousands and thousands of tables on Wikipedia. So are various sorting instructions. And you should explain such reverts on the talk page BEFORE deleting something as common as sorting tables. It was hard work to make this table sortable. --Timeshifter (talk) 13:36, 30 March 2015 (UTC)


 * With over 27,000 edits I could hardly be considered a newbie. Moving forward, can you put sorting arrows into the table heading?  If that's doable, and if you're willing to do it consistently for all tables in the article, I'd say go for it. &mdash; Dsimic (talk | contribs) 13:38, 30 March 2015 (UTC)


 * The reason to have a separate row of sorting headers in this case is because it is a wide table. See the relevant section of Help:Sorting. Section currently titled: "In a narrow space: sorting buttons in a separate row". I have edited Help:Sorting extensively. If the sorting arrows are put in the text cells, then the text cells are wider, and more of the table extends past the right side of the screen on narrower screens. I just did the math, and I have around 125,000 edits total on Wikipedia, Commons, other Wikimedia Projects, Wikia, and Shoutwiki. --Timeshifter (talk) 13:53, 30 March 2015 (UTC)


 * I've read that guideline, but I don't see that as a valid argument, simply because only a few columns would be widened by adding the sorting arrows. &mdash; Dsimic (talk | contribs) 13:58, 30 March 2015 (UTC)


 * Believe me, it adds up. It really irritates a lot of people to have to scroll horizontally. It can be hard enough to have to follow a column down past the bottom of the screen, and then have to remember the column heading. It is easy to mix up columns. To add horizontal scrolling to the mix makes it doubly confusing. The less the better. --Timeshifter (talk) 14:05, 30 March 2015 (UTC)


 * I already have to scroll on a 13-inch screen, and I don't complain. Why are you against using an  note?  It goes along with your "the less the better" approach. &mdash; Dsimic (talk | contribs) 14:16, 30 March 2015 (UTC)


 * , are you willing to discuss this further? &mdash; Dsimic (talk | contribs) 18:01, 31 March 2015 (UTC)


 * I am taking this off my watchlist. There are many other article editors that appreciate sorting more than you do. So why stress myself over any one particular article. I originally added the sorting to satisfy my own needs while researching wattage, speed, price, etc. of CPUs. --Timeshifter (talk) 21:29, 2 April 2015 (UTC)


 * I appreciate everyone's work, but discussing the things and reaching reasonable compromises is the key. &mdash; Dsimic (talk | contribs) 05:56, 5 April 2015 (UTC)

"Thermal problems" section
Hey ! I've "Thermal problems" section  earlier, and I'll try to explain that further. The content this section provided is somewhat not-so-encyclopedic, as it's based on one source and a few forum posts. I know, it's all most probably true, and I've watched numerous Haswell delidding videos on YouTube myself – but to me, it might be better to leave that on YouTube instead of incorporating it into a Wikipedia aricle. At the same time, improved TIM is already covered in section. Hope you agree, and I'm more than open for further discussion. &mdash; Dsimic (talk | contribs) 01:31, 29 August 2014 (UTC)


 * Dude, the TIM is ***NOT*** the issue, and NEVER was, and this has been scientifically proven. The problem is the gap between the top of the die and the IHS.  This section reads like the marketing literature which says the TIM is the problem without telling people that the IHS does not physically even touch the die.  This problem PERSISTS in Devil's Canyon.  Average temperature decrease seen as a result of delidding a Devil's Canyon is on the order of 10-20C, in extreme cases, up to 30C.  The i7-4790K I am typing this from (4.7 GHz @ 1.295Vcore / 4.3 GHz @ 1.200Vuncore) saw a temperature drop of between 14C and 16C simply by delidding.  The delidding removes the gap by getting rid of the true cause of the problem, the epoxy holding the IHS down, which apparently lifts the IHS as it cures. See:   Is this page an encyclopedia of knowledge, or marketing to cover Intel's ass? Oh, and although I don't have the reference handy at the moment, the OFFICIAL explanation is that since the Ivy Bridge shrink, the mainstream CPUs are too small to handle the heat of soldering the die to the IHS without a large number of them cracking, thus the use of the TIM and excessive epoxy.  LGA 2011 and 2011-3 are large enough dies that this is not an issue.  The gap issue is of serious enough importance on the K SKUs (or mainstream SKUs in SFF chassis) that it seriously needs mention in this entry. People researching a USD$330 purchase need to have the correct information. The cure to the problem is delidding, remove the TIM and epoxy residue, protect the VRMs with liquid electrical tape or clear nail polish, replace the TIM on the die with a liquid metal TIM, of which there are now multiple manufacturers (Coolaboratory's Liquid Pro and Liquid Ultra, Gelid's Indigo Extreme), and return the IHS to it's position on top of the die, which now sits directly on top of and in contact with the die. As it sits, this article is giving patently false information concocted by Intel's MARKETING department to DECEIVE people into thinking that the earlier issue with Ivy Bridge and Haswell mainstream SKUs has been solved.  Is Wikipedia in the deception business (a lot of people will give a simple yes to that on probably 20% of the pages at this site)?  Given the leaked picture of the die of the i7-5775C, it is plainly obvious that this problem does extend to the Broadwell as well, and will probably extend to the Skylake as well.  The basic problem is die size, so, unless they increase the transistor budget to increase the size of the mainstream dies (unlikely), this will be an issue for the foreseeable future.  Currently, Wikipedia is three Intel generations behind on telling people about this problem that has been confirmed by many thousands of people worldwide. 69.49.217.158 (talk) 09:19, 15 May 2015 (UTC)


 * Here is a proposed add-in section: "Although the TIM improvement, and especially the use of less epoxy, did make the notorious IHS to Die gap smaller, the gap itself, and it's thermal issues that have existed since the Ivy Bridge shrink on the mainstream SKUs still persists, often to the same extent as in Haswell. An Intel Engineer went public [reference] explaining that the Ivy Bridge and subsequent shrinks made the mainstream dies too small to solder to the IHS without excessive numbers of dies cracking as a result. At normal stock speeds, properly cooled, this is not normally a problem, but in Small Form Factor (SFF) Chassis, and in overclocking, this is a serious issue that has been solved by a procedure known as "delidding", which removes the gap completely, resulting in increased longevity as a result of near-perfect heat transfer to the IHS, although it does void the warranty. [references to above cited encyclopedic sources on the subject]" 69.49.217.158 (talk) 10:06, 15 May 2015 (UTC)


 * Is it "encyclopedic" to accept marketing claims over verifiable experience? I don't see any evidence that "improved TIM" was successful in reducing temperatures. The problem persisted. That is the experience of computer enthusiasts. It may be difficult under the Wikipedia citation system though to find an acceptable source for this. We are left with a situation where published but incorrect information is perpetuated. Intel did put forward a number of explanations regarding the cause of high temperatures, including the one cited in the post above. Seasalt (talk) 12:28, 15 May 2015 (UTC)


 * As we know, Wikipedia requires reliable sources and forum posts aren't considered as such. Sorry, that's how it works.  By the way, how do you know that the 0.06 mm gap between the die and heat spreader isn't there on purpose to compensate for thermal stresses during the CPU operation, for example? &mdash; Dsimic (talk | contribs) 13:52, 15 May 2015 (UTC)


 * Because the delidding/relidding process removes thermal stresses. This is Thermal management 101. The annealing temperature of single-crystal silicon is so high it would literally fry any circuit on it.  Try "A Heat Transfer Textbook" (Lienhard and Lienhard, Third Edition, 2004, Phlogiston Press) for an explanation.  Also the sloppiness, and wide variation points simply to a well known principle of how epoxy hardens, this sloppiness and variation is seen in practice.  If it were to account for some undocumented (anywhere) thermal issue where MORE heat is needed, it would require uniformity and tight tolerances.  Still trying to find that source on the Intel engineer, I have it or had it.  Also, there are now several companies doing this as a service.  "Silicon Lottery" is such a company, Aeri, others...  I've seen that quoting marketing literature and sites is acceptable here, correct? 69.49.217.158 (talk) 18:46, 15 May 2015 (UTC)


 * Do thermal industry pubs count? "Wind-Tunnel Cooled Computer May Help Cure Cancer", ("Electronics Cooling", Jan. 4, 2013) 69.49.217.158 (talk) 19:13, 15 May 2015 (UTC)


 * Perhaps I didn't write it clearly enough, sorry. How do we know that the 0.06 mm gap between the die and heat spreader isn't there to compensate for thermally induced expansion of materials making up the whole processor?  I'm by no means an expert in that area, but many things aren't as straightforward as they seem at the first look. &mdash; Dsimic (talk | contribs) 19:23, 15 May 2015 (UTC)


 * First, the gap is not consistent, and is proportional to the gobbing of epoxy, thus such a wide bell curve of deltas (mine was actually at the mean) from under 10C all the way to 30C. Second, this has been an issue for MANY years.  "Four Decades of Research on Thermal Contact, Gap, and Joint Resistance in Microelectronics", (Yovanovich, IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES, VOL. 28, NO. 2, JUNE 2005) 69.49.217.158 (talk) 19:28, 15 May 2015 (UTC)


 * Hm, when looked at by a non-expert in the area such as myself, it all pretty much makes sense. Also, Intel probably wants its CPUs to have as less redundant cooling potential as possible, as that reduces their overclokability and forces people to buy more expensive variants if higher operating frequencies are desired.  However, we'd need reliable sources and, as I already wrote earlier, forum posts unfortunately aren't considered as such. &mdash; Dsimic (talk | contribs) 19:48, 15 May 2015 (UTC)


 * Well, I'm still searching my links and the net for authoritative sources acceptable here. One problem is that such companies actively use Bush-style cutoff tactics against people who speak of things they would rather avoid discussion on (I wish Obama would do what Bush did to certain "Journalists", instead of just ridiculing them).  The proposed text clearly implies that this is largely a factor only on the K SKUs and in the SFF use-case where thermal issues rear their ugly head the most.  For the standard SKUs in larger well-ventilated cases, with aftermarket air or water cooling solutions, this is not an issue.  Unfortunately, it is an issue for their most expensive chips most suited to these two use-cases. The upcoming Broadwell i7-5775C may indeed produce references to the problem that would be considered "reliable sources" here, as given the specs, and the delidded chip picture leaked this week, it's obvious that to get anywhere close to i7-4790K performance, they will indeed have to be delidded, meaning more mainstream pubs will be referencing the need to do so. Let's call that an educated guess.  69.49.217.158 (talk) 22:19, 15 May 2015 (UTC)

Wrong classification
I believe these cpu : 5820K, 5930K , 5960X are not Haswell , they are Haswell-E. — Preceding unsigned comment added by 87.71.48.161 (talk) 09:18, 8 May 2016 (UTC)


 * They are still based on the Haswell microarchitecture. &mdash; Dsimic (talk &#124; contribs) 01:56, 3 June 2016 (UTC)