Talk:High Precision Event Timer

HPET memory address options
My motherboard has 4 options what do they mean?
 * FED00000h default
 * FED01000h
 * FED02000h
 * FED03000h

Identifying systems with HPET
A rather obvious question I came here for that is currently unaddressed in this article is: how do you know if a system includes an HPET? After all, regardless of what OS you have, you can't use HPET if its hardware isn't there. Is the HPET a separate IC? Is it incorporated into motherboard support chips? Are there CPU-based associations? I didn't notice anything in the two supporting documents that specifically addressed real-world implementations of this functionality. ~ Jeff Q (talk) 18:57, 24 September 2007 (UTC)


 * Some initial hints: it appears to be incorporated into at least one southbridge (ATI's SB600), which I guess makes sense because southbridges handle real-time clock circuitry. Someone also claims HPET is support in the VIA 8237 but not the 8235. ~ Jeff Q (talk) 19:13, 24 September 2007 (UTC)

This is helpful - but is there anything in dmesg output or cpu flags which could indicate this? informedbanker (talk) 01:09, 16 February 2008 (UTC) —Preceding unsigned comment added by Informedbanker (talk • contribs) 01:06, 16 February 2008 (UTC)

Yeah, does my hardware support it? 85.76.120.94 (talk) 09:58, 12 April 2010 (UTC)

Try this in a linux terminal, grep hpet /proc/timer_list, or alternatively you could just look in /proc/timer_list. You should see something like this (set_next_event: hpet_legacy_next_event) and (set_mode:hpet_legacy_set_mode).

Replacing Timers
"HPET is meant to supplement and replace the 8254 Programmable Interval Timer (PIT) and the Real-time clock's (RTC) periodic interrupt function" How is this done, e.g. in circuitry, the BIOS, the OS? -- AzzAz (talk) 20:31, 28 February 2008 (UTC)

What is it?
The very least you should say if it is a KIND OF HARDWARE, or a SPECIFIC HARDWARE. 89.139.171.186 (talk) 15:00, 18 April 2008 (UTC)

32 bit or 64 bit
The link to the Microsoft site states, that 64-bit HPETs will be used in 32-bit mode, so that means that I can set it to 32-bit in the BIOS as well. I wonder whether at least 64-bit Windows OSs use the 64-bit timer registers? ~ Spacy —Preceding unsigned comment added by 92.193.80.110 (talk) 09:55, 28 September 2008 (UTC)

What I did get yet and should be tested:
HPET IO spaces in C style (numbers are #)


 * 1) define	HPET_0_MMIO			0xFED00000 Base address
 * 2) define	HPET_1_MMIO			0xFED80000 Base address

//000-007h  General Capabilities and ID Register          Read Only   Offset
 * 1) define	General_Cap_ID_low		0x0
 * 2) define	General_Cap_ID_high		0x4
 * 3) define	General_Cap_ID_64		0x0

//bit 14	Reserved
 * 1) define	REV_ID				0x00000000000000FF		//bit 0..7	Revision of implemented functions
 * 2) define	NUM_TIM_CAP			0x0000000000001F00		//bit 8..12	Number of the last timer
 * 3) define	COUNT_SIZE_CAP		0x0000000000002000		//bit 13	0=32 bit main counter, 1=64 bit
 * 1) define	LEG_RT_CAP			0x0000000000008000		//bit 15	1=support of Legacy Replacement Route Capable option
 * 2) define	VENDOR_ID			0x00000000FFFF0000	//bit 16..31	like a PCI function
 * 3) define	COUNTER_CLK_PERIOD	0xFFFFFFFF00000000	//bit 32..64	Main counter clock source in 10^-15 seconds (0x5F5E100 = 100 ns)

//008-00Fh  Reserved

//010-017h  General Configuration Register                Read/Write
 * 1) define	General_Conf_low		0x10
 * 2) define	General_Conf_high		0x14
 * 3) define	General_Conf_64		0x10

//bit 2..64	Reserved
 * 1) define	ENABLE_CNF			0x0000000000000001		//bit 0		Enables clock source for the chip
 * 2) define	LEG_RT_CNF			0x0000000000000002		//bit 1		0=individual setings for each timer are used

//018-01Fh  Reserved

//020-027h  General Interrupt Status Register             Read/Write Clear
 * 1) define	General_Int_Status_low	0x20
 * 2) define	General_Int_Status_high	0x24
 * 3) define	General_Int_Status_64		0x20

//bit 32..64	Reserved
 * 1) define	T0_INT_STS			0x0000000000000001		//bit 0	Timer_0 interrupt is active, writing a 1 to this bit will toggle the bit to 0
 * 2) define	T1_INT_STS			0x0000000000000002		//bit 1	Timer_1 - same as above
 * 3) define	T2_INT_STS			0x0000000000000004		//bit 2	Timer_2 - same as above
 * 4) define	T3_INT_STS			0x0000000000000008		//bit 3	Timer_3
 * 5) define	T4_INT_STS			0x0000000000000010		//bit 4	Timer_4
 * 6) define	T5_INT_STS			0x0000000000000020		//bit 5	Timer_5
 * 7) define	T6_INT_STS			0x0000000000000040		//bit 6	Timer_6
 * 8) define	T7_INT_STS			0x0000000000000080		//bit 7	Timer_7
 * 9) define	T8_INT_STS			0x0000000000000100		//bit 8	Timer_8
 * 10) define	T9_INT_STS			0x0000000000000200		//bit 9	Timer_9
 * 11) define	T10_INT_STS			0x0000000000000400		//bit 10	Timer_10
 * 12) define	T11_INT_STS			0x0000000000000800		//bit 11	Timer_11
 * 13) define	T12_INT_STS			0x0000000000001000		//bit 12	Timer_12
 * 14) define	T13_INT_STS			0x0000000000002000		//bit 13	Timer_13
 * 15) define	T14_INT_STS			0x0000000000004000		//bit 14	Timer_14
 * 16) define	T15_INT_STS			0x0000000000008000		//bit 15	Timer_15
 * 17) define	T16_INT_STS			0x0000000000010000		//bit 16	Timer_16
 * 18) define	T17_INT_STS			0x0000000000020000		//bit 17	Timer_17
 * 19) define	T18_INT_STS			0x0000000000040000		//bit 18	Timer_18
 * 20) define	T19_INT_STS			0x0000000000080000		//bit 19	Timer_19
 * 21) define	T20_INT_STS			0x0000000000100000		//bit 20	Timer_20
 * 22) define	T21_INT_STS			0x0000000000200000		//bit 21	Timer_21
 * 23) define	T22_INT_STS			0x0000000000400000		//bit 22	Timer_22
 * 24) define	T23_INT_STS			0x0000000000800000		//bit 23	Timer_23
 * 25) define	T24_INT_STS			0x0000000001000000		//bit 24	Timer_24
 * 26) define	T25_INT_STS			0x0000000002000000		//bit 25	Timer_25
 * 27) define	T26_INT_STS			0x0000000004000000		//bit 26	Timer_26
 * 28) define	T27_INT_STS			0x0000000008000000		//bit 27	Timer_27
 * 29) define	T28_INT_STS			0x0000000010000000		//bit 28	Timer_28
 * 30) define	T29_INT_STS			0x0000000020000000		//bit 29	Timer_29
 * 31) define	T30_INT_STS			0x0000000040000000		//bit 30	Timer_30
 * 32) define	T31_INT_STS			0x0000000080000000		//bit 31	Timer_31

//028-0EFh  Reserved

//0F0-0F7h  Main Counter Value Register                   Read/Write
 * 1) define	Main_Counter_low		0xF0
 * 2) define	Main_Counter_high		0xF4							special read
 * 3) define	Main_Counter_64		0xF0


 * 1) define	MAIN_COUNTER_VAL	0xFFFFFFFFFFFFFFFF	//bit 0..64	Main counter value

//0F8-0FFh  Reserved


 * 1) define	Timer_03				0x160
 * 2) define	Timer_04				0x180
 * 3) define	Timer_05				0x1A0
 * 4) define	Timer_06				0x1C0
 * 5) define	Timer_07				0x1E0
 * 6) define	Timer_08				0x200
 * 7) define	Timer_09				0x220
 * 8) define	Timer_10				0x240
 * 9) define	Timer_11				0x260
 * 10) define	Timer_12				0x280
 * 11) define	Timer_13				0x2A0
 * 12) define	Timer_14				0x2C0
 * 13) define	Timer_15				0x2E0
 * 14) define	Timer_16				0x300
 * 15) define	Timer_17				0x320
 * 16) define	Timer_18				0x340
 * 17) define	Timer_19				0x360
 * 18) define	Timer_20				0x380
 * 19) define	Timer_21				0x3A0
 * 20) define	Timer_22				0x3C0
 * 21) define	Timer_23				0x3E0
 * 22) define	Timer_24				0x400
 * 23) define	Timer_25				0x420
 * 24) define	Timer_26				0x440
 * 25) define	Timer_27				0x460
 * 26) define	Timer_28				0x480
 * 27) define	Timer_29				0x4A0
 * 28) define	Timer_30				0x4C0
 * 29) define	Timer_31				0x4E0

//00-07h  Timer (N) Configuration and Capability Register Read/Write
 * 1) define	T_Conf_Cap_low		0x0
 * 2) define	T_Conf_Cap_high		0x4
 * 3) define	T_Conf_Cap_64			0x0

//bit 0	Reserved //bit 7	Reserved //bit 16..31	Reserved
 * 1) define	T_INT_TYPE_CNF		0x0000000000000002		//bit 1	0 = edge triggered, 1 = level triggered
 * 2) define	T_INT_ENB_CNF		0x0000000000000004		//bit 2	1 = interrupts are enabled for this timer, 0 = disabled
 * 3) define	T_TYPE_CNF			0x0000000000000008		//bit 3	1 = periodic, 0 = single shot
 * 4) define	T_PER_INT_CAP		0x0000000000000010		//bit 4	Read only bit, 1 = periodic mode is supported
 * 5) define	T_SIZE_CAP			0x0000000000000020		//bit 5	Timer's comperator size, 1 = 64 bit, 0 = 32 bit
 * 6) define	T_VAL_SET_CNF		0x0000000000000040		//bit 6	Writing 1 here loads the the new comperator value next time.
 * 1) define	T_32MODE_CNF		0x0000000000000100		//bit 8	Timer can be set to 32 bit mode, this has no effect on 32 bit timers
 * 2) define	T_INT_ROUTE_CNF		0x0000000000000200		//bit 9..13	Route interrupt to IRQ of the APIC if FSB interrupts are not enabled
 * 3) define	T_FSB_EN_CNF			0x0000000000004000		//bit 14	If FSB interrupts are supported it can be set. the T_FSB_ROUTE registrer will be used
 * 4) define	T_FSB_INT_DEL:CAP		0x0000000000008000		//bit 15	If this read only bit is set then this timer supports FSB interrupt delivery.
 * 1) define	T_FSB_INT_DEL:CAP							//bit 32..64	Routing table to possible IRQs of the APIC.

//08-0Fh  Timer (N) Comparator Value Register             Read/Write
 * 1) define	T_Comparator_low		0x8
 * 2) define	T_Comparator_high		0xC
 * 3) define	T_Comparator_64		0x8

//10-17h  Timer (N) FSB Interrupt Route Register          Read/Write
 * 1) define	T_FSB_Int_Route_low		0x10
 * 2) define	T_FSB_Int_Route_high	0x14
 * 3) define	T_FSB_Int_Route_64		0x10


 * 1) define	T_FSB_INT_VAL							//bit 0..31	FSB interrupt message
 * 2) define	T_FSB_INT_ADDR							//bit 32..64	FSB interrupt location the message is written to

//18-1Fh  Reserved

//Table 2 Memory-Mapped Registers

How the FSB interrupt mechanism works I don't know

Introduction
When were HPETs introduced?

Any BIOS/Motherboard designers care to comment?
I contributed some stuff to this article (as 86.140.252.28) based on research and experimentation using XP both on an AMD and an Intel box, both of which were intriguingly quoting HPET even though the 15MHz Intel device was not being used. However, I could only do this from the point of an application software engineer with access to hardware and software specifications and Microsoft online documentation. It would be really useful if someone with insider knowledge of motherboard design and BIOS writing could clarify how the connectivity issues are resolved: For instance, is the manner in which available devices in the SouthBridge chip are used to provide the "virtual" timing devices negotiable only at track wiring level (e.g. could the HPET in fact be emulating RTC/PMTimer in hardware; is it still seperately connected and wired; or is it ruled out by common signal paths when normal RTC/PMTimer usage is intended?). Is it the BIOS that tells the HAL what is available, or can the HAL actually make effective runtime wiring (connectivity) descisions? If Windows XP doesn't even ask about a true hardware HPET, then is it possible that a special device driver could be written to allow its use by software applications that are aware of that driver? Or would that again suffer the problem that no seperate and independant interrupt vector could be set up? Can somebody (or has somebody) with driver writing experience create (created) such a driver for Windows XP? — Preceding unsigned comment added by Alex Tidmarsh (talk • contribs) 20:49, 26 December 2011 (UTC)

Use in Non Windows Operating Systems.
You do know that Windows is not the only Operating System out there. Why aren't there notes on how this hardware feature is used in other Operating Systems, such as Linux?--Robert Wm &#34;Ruedii&#34; (talk) 06:11, 10 September 2013 (UTC)
 * If you know of other uses add them per WP:BOLD. The HPET was largely a Microsoft project; they stongly advocated it in a 2002 document (which also dissed most alternatives) so don't be so surprised who ended up using it. Someone not using his real name (talk) 13:23, 13 February 2014 (UTC)
 * Linux has been using the HPET almost since its inception. The problem is a substantial part of the computing universe, as well as this "encyclopedia," is inhabited by people who don't know anything about computer technology unless it says Microsoft on it.
 * 38.69.12.5 (talk) 04:37, 12 April 2017 (UTC)
 * Wikipedia isn't finished yet, if you feel some information is missing, add it! Respectfully, InsaneHacker (💬) 12:48, 22 August 2017 (UTC)

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