Talk:Interrupt descriptor table

IVT vs IDT
Well, there is no "IDT" on an 8086 or a processor operating in real mode... It's called an IVT and has a greatly different structure. On >= 80286 the IVT address in real mode _IS_ loaded in the IDTR (no such register is present < 80286). Technically.


 * There is no architected way to change the real-mode IDTR on a 286, but it may be possible via LOADALL. At any rate, on a 386+ the real-mode IVT can certainly move around and almost certainly is also subject to the IDTR limit. Reducing the IDTR limit to zero and triggering an interrupt is typically an excellent way to cause processor shutdown. Codegen86 (talk) 19:21, 4 July 2012 (UTC)

Suggesting removeing or replacing the table in the article
There is a table in the article which describes interrupts installed when running (some version of) Linux. I see little relevance to the general nature of the IDT in the table -- it is entirely Linux specific.

I therefor suggest removing it completly or replaceing it with a table which describes the 32 reserved interrupt vectors, which may be used by the processor.

Proposing merger into sub-section of "Interrupt Vector Table" article
The "Interrupt Vector Table" is a concept that is common across multiple processor architectures. This article is about a specific implementation of this concept on a specific architecture, and therefore, is not appropriate as a replacement for the generalized "Interrupt Vector Table" article that was removed and turned into a redirect. The "Interrupt Vector Table" article has been restored, and should be further expanded upon in terms of the general idea. At the same time, the information should be consolidated by having specific architecture implementations (such as the one described by this article) condensed and turned into smaller sections within the generalized article 75.84.15.136 (talk) 01:36, 5 December 2011 (UTC)
 * Interrupt Vector Tables are used in the real addressing mode: the structure just contains addresses of Interrupt Service Requests. In the protected mode, the structure is more complicated and it's called the Interrupt Descriptor Table. The external link I just added to the article has all the details. Older architectures were only real mode, so they used the term IVT, but newer ones have both real and protected mode (and use both because they have to boot using real mode). Each of these articles Interrupt Descriptor Table and Interrupt vector table are too narrow of a topic to deserve a separate article. In fact, there are a ton of tiny articles on the topic of interrupts, most of which should be merged into maybe two or three articles. Here's a partial list:


 * Advanced Programmable Interrupt Controller (APIC)
 * BIOS interrupt call
 * Event-driven programming
 * INT (x86 instruction)
 * Inter-processor interrupt (IPI)
 * Interrupt
 * Interrupt handler
 * Interrupt latency
 * Interrupts in 65xx processors
 * Non-maskable interrupt (NMI)
 * Programmable Interrupt Controller (PIC)
 * Ralf Brown's Interrupt List

Although this should probably be discussed on at Talk:Interrupt.  Sparkie82 ( t • c )  04:36, 6 December 2012 (UTC)

physical address??
The article now says:

'''The protected mode IDT may reside anywhere in physical memory. The processor has a special register (​IDTR​) to store both the physical base address and the length in bytes of the IDT. '''

Isn't this wrong? Doesn't the IDTR (loaded with the LIDT instruction) contain a virtual, not physical, address? The spec refers to it as a "linear address" - which is a virtual, not physical - address. Nyh (talk) 11:43, 7 June 2012 (UTC)


 * Yes, it's wrong. The AMD64 spec talks about virtual addresses being used as GDTR/IDTR/LDTR base. Hence the address is subject to paging and it is common for operating systems to use an IDTR base which is much higher in the (virtual) address space than the top of physical memory. Codegen86 (talk) 19:34, 4 July 2012 (UTC)

Interoperability?
Probably a dumb newbie question, but as I understand it, there are two distinct IVT formats used for real mode versus protected mode, as elucidated in the article. It is also my understanding that processors capable of protected mode operations can support real mode. So my question is: how is this managed? Are there realistic scenarios where two distinct tables are required simultaneously, or is there some standard way of merging the two distinct copies? Must they point to the same target handlers? I presume that the OS usually takes care of this, and picks a method, but that's just a semi-educated guess. 70.247.162.60 (talk) 03:15, 11 November 2015 (UTC)

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