Talk:LPDDR

LPDDR vs multichannel DDR3 SODIMM
"LPDDR3 will debut in 2013, running at 800 MHz DDR (1600 MT/s), offering bandwidth comparable to PC3-12800 notebook memory in 2011 (12.8 GB/s of bandwidth).[6] However, even though it offers the same memory bandwidth as notebook memory from 2011, mobile CISC processors still operated at even greater bandwidth by utilizing dual channel memory, effectively doubling the bandwidth.[citation needed][dubious – discuss] More accurately this will allow low power RISC processors to have the same memory bandwidth as mobile CISC processors from around 2006–2007."

Why 'citation' and 'dubious'? Many notebook CISC CPUs have multichannel DDR3 controller, e.g. List_of_Intel_Core_i7_microprocessors (intel models of 2010-2011; same for i3 and i7): And AMD mobile 2010-2011: List_of_AMD_mobile_microprocessors, based on S1G4 socket with dualchannel DDR3 "socket supports dual-channel DDR3 memory with data rates up 1333 MHz"; next socket FS1 of 2011-2012 has 2 channel memory too:  "FS1 works with dual-channel DDR3 memory with data rates up 1600 MHz".
 * "Clarksfield" - 2 × DDR3-1333
 * "Arrandale" - 2 x DDR3-1066 or 2 × DDR3-800
 * "Sandy Bridge (Dual-Core)" - 2 x DDR3-1066/1333
 * "Sandy Bridge (Quad-Core)" (32 nm) - 2 x DDR3-1066/1333/1600

So, I think, this is clear enough that normal 2010-2011 notebooks (not netbooks) were capable of multi-channel (dual-channel) DDR3 with the same MT/s, so double bandwidth of single-channel LPDDR3. The only RS that can be needed here is RS for using single-channel LPDDR in most of smartphones/tablet PC. E.g. Tegra platform had single-channel memory in Tegra 2, Tegra 3 and Tegra 4i; only Tegra 4 has dual-channel "LPDDR3 up to 933". Snapdragon 600 and 800 are dual-channel too. ]Apple Ax are from Single-channel LPDDR up to Quad-channel LPDDR2. Exynos 5 are dualchannel LPDDR3, OMAP 5 is dualchannel LPDDR2.

Many multichannel mobile ARM SoCs are with 32-bit width memory bus, while notebook DDR3 SDRAM (SODIMM) is still 64 bit wide. `a5b (talk) 20:26, 23 April 2013 (UTC)

LPDDR-x vs DDR-x
Are the LPDDR memory specs derived sequentially, or each derived from the full power DDR specs? Put another way: is LPDDR4 derived from DDR4 or LPDDR3? This is not clear to me from the article. Dbsseven (talk) 18:53, 15 January 2018 (UTC)

External links modified (February 2018)
Hello fellow Wikipedians,

I have just modified 2 external links on Mobile DDR. Please take a moment to review my edit. If you have any questions, or need the bot to ignore the links, or the page altogether, please visit this simple FaQ for additional information. I made the following changes:
 * Added archive https://web.archive.org/web/20130728110139/http://denalimemoryreport.com/2012/06/13/want-a-quick-and-dirty-overview-of-the-new-jedec-lpddr3-spec-eetimes-serves-it-up/ to http://denalimemoryreport.com/2012/06/13/want-a-quick-and-dirty-overview-of-the-new-jedec-lpddr3-spec-eetimes-serves-it-up/
 * Added archive https://web.archive.org/web/20130429232326/http://www.chipworks.com/blog/recentteardowns/2013/04/25/inside-the-samsung-galaxy-s4/ to http://www.chipworks.com/blog/recentteardowns/2013/04/25/inside-the-samsung-galaxy-s4

When you have finished reviewing my changes, you may follow the instructions on the template below to fix any issues with the URLs.

Cheers.— InternetArchiveBot  (Report bug) 04:10, 3 February 2018 (UTC)

LPDDR5
On July 17th 2018 Samsung Semiconductor announced the first 8GB LPDDR5 Mobile DRAM chip based on the 10 nanometer architecture, the chip use less power and has a higher bandwidth than the preceding LPDDR4/LPDDR4X.NIK3 13:32, 1 November 2018 (UTC)

Potential Missing Change In Standards
https://www.jedec.org/news/pressreleases/jedec-publishes-new-and-updated-standards-low-power-memory-devices-used-5g-and-ai

"...announced the publication of JESD209-5B, Low Power Double Data Rate 5 (LPDDR5). JESD209-5B includes both an update to the LPDDR5 standard that is focused on improving performance, power and flexibility"

There seems to be a lack of clarity and no mention that there was an original LPDDR5 & now a refreshed standard/spec for it alongside the optional stuff that is mandatory in LPDDR5X. The source is already used in article Dasein (talk) 20:19, 27 August 2021 (UTC)

LPPDR Android
LPPDR Android optimisation de optimal optimum charge rapidement les composants qui ne chauffent pas pour faire du gaming bonne journée optimisation optimal optimum charge rapidement fonctionne bien en vert technologie durablement pour faire du gaming bonne journée Musicientst66 (talk) 06:30, 21 May 2024 (UTC)

Comments by IP user
I'm pasting the following commentary for 95.67.192.238. This commentary was originally posted on the main article. Please refer to their talk page for further explanation. Note: The user is referring to the "Bus width" section in their comments. "proposal to the Wikipedia community to check the table above, the data obtained from the actual Samsung and Micron catalog on 6.06.2024 from semiconductor.samsung.com and micron.com official sites listing LPDDR3, LPDDR5 and LPDDR5 with a 64 bit width data (table contains a maximum of 32 bit data tire for LPDDR3/5/5X, also parameter "Maximum density (bit)" changed on "Maximum data bit width") contained models with its speeds and density not exceeding the values of the table above What makes the recommendation update table: Micron MT62F2F2F2F8ZA-020 WT: C - 128 Gbit density at 9600 MT/S lpddr5 Samsung K3LKDKD0CM-BGCP lpddr5 - 144 Gbit density 6400 MT/s  Samsung K3Klele0DM-BGCU lpddr5x - 144 Gbit density 8533 MT/s Samsung K3QFAFA0CM-AGCF lpddr3 - 64 Gbit density at 1866 MT/s applying 64 bit width data, but the previous models in the catalog cannot be found, its were removed from sites. In the catalogs there are models for various LPDRs as 16 and 32 and 64 bit data width." Urban Versis 32KB ⚡ (talk / contribs) 01:00, 10 June 2024 (UTC)