Talk:MOSFET/Archive 2

How it works
Brews, I see you're working on the description of how it works. I never liked that idea that the voltage from gate to substrate is the main or only thing that matters in terms of channel creation; I understand that it does control inversion, accumulation, depletion region depth, etc. in a MOS cap, but in a transistor that has a source, the mobile channel charge comes from the source, not from the substrate. As you know, you can control the source–drain current by tying the gate and substrate together and moving the source relative to those (within limits, as you don't want to forward bias your isolation junctions much), effectively using the substrate as a "back gate". So the description you just edited is still not very satisfying in that regard. Looking at it another way, if you fix the S, G and D voltages, and look what happens when you move the B voltage, it's exactly opposite of what is suggested by saying that "a voltage drop between the oxide-insulated gate electrode and its substrate induces a conducting channel." In other words, it's the surface potential (relative to the source) that most affects the current, not the drop from gate to substrate. Yes? Dicklyon (talk) 23:41, 22 March 2012 (UTC)


 * Hi Dick: A full explanation would be a bit much in the intro. I don't think a simple form of words covers the matter. The full explanation requires the concept of quasi-Fermi levels. The bulk has one Fermi level and the source and drain (assume they are shorted for argument's sake) have theirs. The two are separated by the reverse bias between source and substrate.


 * For a long channel device, where the pn-junction depletion regions are small compared to the source-to-drain separation, the bulk Fermi level controls matters at midchannel and it looks like an MOS capacitor. However, as the inversion layer becomes established, and extends all across the interface, the Fermi level of the source and drain set the population of the inversion layer.


 * So there is a hand-off as the inversion layer strengthens. If there is no reverse bias and the two Fermi levels are the same, the MOS capacitor analysis continues to hold good. If now a reverse bias is applied from source to substrate, the Fermi level in the inversion layer drops, so threshold for formation of the full inversion layer is delayed to larger gate-to-substrate voltages when reverse bias is present.


 * The hand-off is muddier for a short-channel device, where all three electrodes interact directly with the full depletion layer, as well as via the channel.


 * How would you like to handle this matter? Brews ohare (talk) 05:39, 23 March 2012 (UTC)


 * I'd like to say less in the lead; I'd omit the idea of channel inversion, and if we mention gate voltage, make it with respect to source, not bulk. I'm not sure what you mean by "the bulk Fermi level controls matters at midchannel."  Isn't the mobile charge there mostly controlled by what happens at the source?  Dicklyon (talk) 06:06, 23 March 2012 (UTC)


 * Dick, I believe your intuition is on the wrong track. So long as there is no voltage VSB and no VDB, the device behaves like an MOS capacitor and it is the gate-to-substrate voltage VGB that decides whether there is a channel. If there is a channel, say electrons, they can move freely between the channel and the source or drain; the Fermi level is the same all the way across. However, if we make VSB ( =  VDB) a reverse bias, it lowers this common Fermi level compared to the Fermi level in the bulk. To first order the surface potential is pinned (unaffected at a fixed value conventionally taken as 2&phi;B) so the field in the oxide is unchanged by the reverse bias. But the drop in population of the channel means the charge balance is upset. To satisfy Gauss' law, the oxide field is now balanced by a larger negative depletion layer charge to compensate for the loss of negative channel charge. In math:
 * $$Q_I+Q_D=\kappa \epsilon_0 (\phi_G-\phi_S)/t_{ox} \, $$
 * where &phi;S is pinned at 2&phi;B, QI = inversion layer charge, QD = depletion layer charge. This equation is the same as in the MOS capacitor, but QI is not related the same way to &phi;S, but is reduced by a factor exp(qVSB/kT).Brews ohare (talk) 15:22, 23 March 2012 (UTC)
 * This Boltzmann factor is an exaggeration: one has to do a careful calculation of the effect of the change in Fermi level. Brews ohare (talk) 16:21, 23 March 2012 (UTC)
 * So there is nothing misleading in the intro statement for the simple case of no reverse VSB. The charge in the channel has nothing to do with the source until a reverse bias is applied. Brews ohare (talk) 15:22, 23 March 2012 (UTC)
 * But in the region where the channel is getting charge from the source (that is, any region in which there is a controlled current), the V_gs is what matters most, and the bulk voltage V_bs affects current in the same direction that the gate voltage does, whereas looking at V_gb as controlling suggests that the bulk would work in the other direction. Dicklyon (talk) 15:27, 23 March 2012 (UTC)
 * Dick: The oxide field can be related to VGS, but that is possible only when the channel is present. Otherwise, the oxide field is given as I have indicated in the Gauss' law equation above. So if we are interested in the mechanism behind formation of the channel, we have to go to the Gauss' law equation at midchannel and leave the source out of it.
 * I am not sure what you are saying about the substrate bias. I imagine we agree that reverse bias on the source expands the depletion layer. When there is a channel, VSB affects the Fermi level all through the channel and lowers its population. The expansion of the depletion layer midchannel then stems from the Gauss' law equation above with QI modified by the source VSB. If there is no channel, then VSB has no effect at all and Gauss' law midchannel is as given, but with QI=0.
 * The effect of the source on midchannel is absent until the channel forms to extend the source's influence the full width of the device. If one wants to describe the field effect that forms the channel, one cannot use the VGS formulation because it works only after the channel forms. Brews ohare (talk) 16:06, 23 March 2012 (UTC)
 * A brief look suggests you might find this source helpful. Brews ohare (talk) 17:20, 23 March 2012 (UTC)
 * Brews, I think I get all that, though I'm certainly not the MOS expert that you are. But what I'm saying is that concentrating on channel formation gives the wrong impression in important cases.  In particular, consider the common case of the MOSFET in saturation, (so we can ignore the drain), with a small nonzero current I_ds.  Now, what happens if you change the bulk potential, relative to the other three terminals?  Say you move the voltage up, in an NFET.  This reduces V_gb, so would tend to make less of a channel.  But the effect is that it increases the current, since it raises the surface potential and allows more electrons to enter from the source.  This is the sense in which I think concentrating on channel formation is misleading.  The source current is controlled not so much by the existence of a channel, but by the relative barrier height that allows electrons to enter.  Admittedly, my thinking on this may be more relevant in the subthreshold region where the surface potential is most relevant, and where there is perhaps no channel in the sense that you mean.  Above threshold, the bulk, or "back gate", continues to affect the current in the same direction that the gate does, not opposite as would be suggested by V_gb being the relevant parameter.  Dicklyon (talk) 17:33, 23 March 2012 (UTC)

The notion of barrier height can be applied in subthreshold, but it does not apply elsewhere. Of course, subthreshold is a very special bias regime, and most circuits don't use the device in that mode. The notion that a barrier limits the current is just not true in normal operation, where the channel behaves like a resistor carrying a current dependent upon VDS and a conductance dependent upon QI. A barrier limitation is a digression in this context. I simply don't grasp the counterintuitive notion that VGB provides the wrong dependence. I think you are ignoring the pinning of the surface potential in strong inversion. The oxide field is therefore fixed when VSB is varied, and the increase in VGB is not due to any change in oxide field but due to the increased depletion depth forced by Gauss' law when QI drops. The notion that varying VB alters the surface potential and thereby affects QI and the current is incorrect outside of subthreshold. It is the Fermi level shift due to VSB that affects QI. Brews ohare (talk) 18:43, 23 March 2012 (UTC)
 * Brews, I realize that you don't have much experience with transistors been used in the subthreshold region, but it's certainly not rare or unusual (and at the drain end, it's always in subtreshold if in saturation, so the resistor model is in applicable in that typical region). My own experience is more with micropower circuits (including substreshold transconductance amplifiers and such) and image sensors (with subthreshold conduction in overflow/antiblooming transistors and other places), and in 4T "loadless" SRAMs with subthreshold load currents.  But if you don't want to look at that region, consider near and above threshold, where substrate bias can be thought of as a way to adjust threshold.  More substrate bias (lower bulk voltage for an nFET) relative to the other terminals raises the threshold voltage, thereby reducing the current, even though it increases V_gb and increases the channel formation, because it also increases the barrier that electrons in the source need to get over to enter the channel.  So lower the bulk voltage lowers the current, contrary to what the channel-formation model suggests.  Yes?  Dicklyon (talk) 18:01, 25 March 2012 (UTC)


 * Dick, thinking about this, I came to the conjecture that perhaps we are looking at different electrodes as the reference.
 * One can look at this from various perspectives: for instance, imagine the gate and source-drain fixed in an nMOS device. The source is reverse biased by driving the substrate negative, VSB > 0. The Fermi level in the channel drops and QI goes down. The oxide field is fixed, so QD increases in magnitude. The potential drop across the depletion layer goes up to about 2&phi;B+VSB. The surface stays at 2&phi;B, the oxide field at (&phi;G-2&phi;B)/tox. Alternatively, the substrate could be held fixed and the source and gate increased by VSB, which is the same situation, but using a different electrode for reference. In this case, if the gate is now brought down to VG from VG+ VSB, we obtain a situation where the reverse bias on the source is obtained by positively biasing the source while keeping the gate and body fixed. Of course the drop in gate voltage means the oxide field goes down. If the channel is still there, its population drops while the depletion layer remains enlarged corresponding to 2&phi;B+VSB. Brews ohare (talk) 16:07, 24 March 2012 (UTC)
 * That's not the issue. See above.   Perhaps consideration of a double-gate MOSFET with no bulk connection will be a useful analogy to explain what I mean about the back gate working in the same direction as the gate,  not opposite to it.  Dicklyon (talk) 18:01, 25 March 2012 (UTC)

Dick, I don't understand you, and you don't understand me. I don't think there is a remedy. Brews ohare (talk) 03:20, 26 March 2012 (UTC) In any event, this discussion concerns the influence of source-to-substrate bias, which has no part in the introduction, and does not impact the reference to the field effect as the underlying mechanism underlying channel formation. Brews ohare (talk) 04:28, 26 March 2012 (UTC)
 * My point is that focusing on "channel formation" also doesn't belong in the lead. Do you agree at least that in an nFET, raising the bulk voltage (relative to constant voltages of the other three terminals) will tend to increase the current, not decrease it?  And do you agree that raising the bulk voltage reduces the "voltage drop between the oxide-insulated gate electrode and its substrate"?  And that that sounds like it causes there to be less of a conducting channel?  In fact, in strong inversion, the bulk potential does very little, due to screening by the charge sheet in the channel, right?  So the conduction is pretty much controlled by Vgs, and Vgb does very little, right?  Dicklyon (talk) 05:23, 26 March 2012 (UTC)
 * Let us begin by clarifying what "increasing" the bulk voltage means. In my mind it would mean forward biasing the source and drain junctions with the substrate. That is a mode hardly every employed in circuits. Is it what you mean? Brews ohare (talk) 12:12, 26 March 2012 (UTC)
 * To reply about the field effect, assuming zero bias across source-substrate and drain-substrate pn-junctions, the analysis at midchannel along a vertical line from the substrate to the gate is identical with that in a 1-D MOS capacitor in every respect. Brews ohare (talk) 12:25, 26 March 2012 (UTC)
 * Yes, that is the direction I meant, but I think I already specified that I meant not so much as to forward-bias the S/D junctions. And I meant from whatever starting point you like, which may have been a negative potential.  And I meant the linearized effect, so the direction could equally be the other way, with the opposite result.  That is, taking the substrate more negative will reduce the current, even though, I agree, the MOS cap analysis suggests that it will make more of a channel.  An example of using the back-gate as an explicit input, with the direction of effect that I'm describing, is here.  And, risking repeating myself for clarification, I'm not arguing that anything you said about channel formation is wrong.  What I'm arguing is that that doesn't give you much insight into the current through the device, which is much more contolled by Vgs, and depends on Vbs in the direction opposite to what a focus on Vgb would suggest.  Do you agree, or disagree, on the direction in which varying the body voltage relative to the other three terminals will affect the current?  That is, that moving the body in the direction of making more of a channel (lower voltage in the case of an nFET) will reduce the current?  And that moving the body up, making less of channel, will increase the current?  Dicklyon (talk) 16:45, 26 March 2012 (UTC)


 * As I agreed earlier, once the inversion layer is formed, it is fine to think in terms of Vgs, because the oxide field all along the channel, including mid-channel is related to Vgs. It is the oxide field that supports the channel and decides its strength. Supposing that the source and drain are not reverse biased and Vgb is increased, then the current does increase all the way from below threshold to above it, as the field effect suggests, so I'd guess you have no problem in this case?


 * So the quandary (?) arises only when reverse bias is applied to the source. Of course, Vgs doesn't change, so it is hard to make the case that Vgs is the controlling factor in this situation. So to handle this case you'd like to see the Vbs effect as a field effect from the substrate as a gate, making a kind of symmetry with the Vgs case. Is that right?


 * With an inversion layer present, for an nMOS device, applying a negative substrate voltage increases the depletion layer charge and lowers the channel density. Vgs is held fixed, so the total drop from gate to body Vgb increases although the current goes down. Your perspective upon this is that the field effect would suggest that a large Vgb means a larger current, not a smaller one, so you'd say the field effect from the gate is the wrong way to look at it. I guess that is what you are aiming at?


 * In the reverse Vbs case, my preference is to maintain the notion of the field effect from the gate, that is, control by the oxide field, and point out that Vbs reduces the QI via a Fermi level shift, so the oxide field expands the depletion layer according to the field effect with reduced QI. The effect of Vbs from this stance is about Vbs sucking charge out of the channel into the source.


 * So, I guess you'd like to avoid the Fermi level argument and find an argument that treats the gate and substrate similarly. I suppose the symmetry of that idea appeals to you. If I'm on the right track, maybe we can continue? Brews ohare (talk) 18:08, 26 March 2012 (UTC)
 * You're right, we're not going to understand each other. Did you look at the paper I linked?  Dicklyon (talk) 04:04, 27 March 2012 (UTC)

Dick: The paper you refer to uses the device in saturation and varies the threshold voltage slightly with a forward substrate bias. The analysis applies assuming the channel is present, so its bearing upon channel formation is nil. This mode of operation is atypical. It will inject current into the source and drain from the substrate, because the junctions are forward biased, and so the device carries a "back-gate" current, unlike the normal front gate that is insulated, and causes no forward bias of the junctions.
 * Questions:
 * Do you agree that the standard MOS capacitor analysis for the field effect applies midchannel if Vsb, Vdb are zero? Vgs plays no role in this analysis, which is in terms of Vgb.
 * Do you understand the standard Fermi level analysis of Vsb effects as I've described them?
 * Why do you want to introduce Vsb ≠ 0 operation in the introductory paragraph? It seems to me that Vsb effects should be presented in the body-effect section, and if that is interesting, the standard Fermi level approach can be compared with alternatives there. Brews ohare (talk) 12:40, 27 March 2012 (UTC)
 * Brews, yes, I agree with the analysis for channel formation midchannel (but if I understand the words "inversion" and "channel" it's only inverted, or only a channel, when there are electrons in the channel, i.e. when the transistor is in an ON state, which is very dependent on source voltage). I sort of understand the Fermi level analysis, and have no problem with that.  And I am NOT suggesting we add any of these complications to the lead.  Rather, I'm suggesting that we simplify the lead by removing the stuff about Vgb and channel formation.
 * Your interpretation of body effect as a slight shift of threshold is entirely consistent with what I've been saying about the direction in which body voltage will affect current, which is in the opposite of the direction in which it affects channel formation.  The current wording here is very confusing:

"In enhancement mode MOSFETs, a voltage drop between the oxide-insulated gate electrode and its substrate induces a conducting channel between the source and drain contacts via the field effect. The term "enhancement mode" refers to the increase of conductivity with increase in a field that adds carriers to the channel, also referred to as the inversion layer."


 * What field adds carriers to the channel? The carriers only come from the source, and increasing the field by lowering the body voltage works against that.  And this "increase of conductivity" concept is only applicable in the space-charge-limited (strong inversion) region, so it ignores the whole  important weak-inversion region where charge travels by diffusion, not by a drift limited by conductivity.  So, I think your approach is somewhat traditional, but thereby is only applicable to the strong-inversion ON region, and even there is misleading about how body voltage will affect current (by suggesting that lowering body voltage to a more negative voltage will increase conductivity, which sounds like it should increase current, when it actually decreases the current, by raising the threshold in your language). Dicklyon (talk) 17:01, 27 March 2012 (UTC)
 * Dick, I'll pick out a few points for reply:
 * if I understand the words "inversion" and "channel" it's only inverted, or only a channel, when there are electrons in the channel, i.e. when the transistor is in an ON state, which is very dependent on source voltage
 * Yes the channel exists in the ON state. In pMOS the channel has holes, in nMOS electrons. Assuming source and body are grounded, the existence of the channel depends only on the gate voltage, and the behavior is the same as the MOS capacitor, where there are no source or drain electrodes. So to say the channel depends upon the source voltage is incorrect in this situation.
 * What field adds carriers to the channel? The carriers only come from the source...
 * By field, oxide field is meant. The carriers in the MOS capacitor come from SRH-generation in the depletion layer, as there is no source. When the oxide field increases, it lowers the conduction band so more of it is available for population by electrons. When a source is present, electrons still can be generated by the SRH mechanism, but as soon as the channel forms, it is much faster to supply them from the source.
 * this "increase of conductivity" concept is only applicable in the space-charge-limited (strong inversion) region, so it ignores the whole important weak-inversion region where charge travels by diffusion
 * This statement is not correct. The "increase in conductivity" is a continuous process, continuous with increasing oxide field, from depletion through weak inversion to strong inversion, just as in the MOS capacitor. The conductivity depends only on the channel population, and not upon either the generation mechanism or the transport mechanism from source to drain.
 * ...is misleading about how body voltage will affect current (by suggesting that lowering body voltage to a more negative voltage will increase conductivity...
 * There is no reason to drag body voltage into this matter, as the channel formation is well-described by the field effect, which is controlled by the gate alone. If you do want to include a discussion of Vsb, then that can be done, but it is a digression so far as channel formation is concerned.
 * If Vsb is to be discussed, that can be done, but it is a separate issue from the field effect from the gate that controls channel formation. If you were to write down the 1-D Poisson equation at midchannel (the equation describing the field effect), the charge term consists of minority carriers and depletion layer charge. The minority carrier density is the same as for the MOS capacitor, but reduced by a factor depending upon Vsb.  That factor stems from the changed Fermi level of minority carriers. It is not an electrostatic effect; the Fermi level is a form of electrochemical potential. The electrostatics are altered midchannel however, because the minority carrier charge term for a given oxide field is decreased due to this Fermi level shift. As a result the calculated band bending across the depletion layer corresponding to a given oxide field from the 1D Poisson equation will be increased, and the depletion layer is wider for a given oxide field when Vsb ≠ 0. That makes the sum of charges per unit area,  QI + QD, the same for the same oxide field, regardless of Vsb, as required by Gauss's law. Brews ohare (talk) 21:11, 27 March 2012 (UTC)


 * If you doubt my statements, take a look at the book I suggested above. Or look at Tsividis. Brews ohare (talk) 21:31, 27 March 2012 (UTC) The Fermi level shift under reverse bias is discussed in P–n_diode for the pn-junction.

More on how it works
a header to break up the long commentary here

Most of your statements I don't doubt. But let me be clear: I'm not proposing we talk about the body voltage in the lead; quite the opposite:  I'm saying we should take it out of lead, where it appears in "a voltage drop between the oxide-insulated gate electrode and its substrate".

The part of what you're saying that still confuses me is about what happens when the source and drain voltage are too high, so they take charge out of the channel, but don't put it in. Then the slow carrier generation will never make much of a channel, as the charges will exit as quickly as they are generated; inversion won't happen, even though the surface potential would happily accommodate carriers there, and the voltage that you think of as producing a conductive channel won't do so. Even at mid-channel, if the source voltage is too high, you'll get no channel, because all your mobile carriers will get away quickly. Right? In that sense, the stuff about channel formation and conductivity seems like just a conventional fiction, not very useful to understanding the current in any region other than strong inversion, and even that is determined more by the source than by the voltages that cause "inversion". I was never in the habit of paying attention to that conventional fiction, since I was working in weak inversion, where it was more troublesome than helpful. The model in the appendix of Carver Mead's Analog VLSI and Neural Systems worked better for that domain, where the back-gate effect is effectively linear and just like the gate in terms of how it modulates the current by moving the barrier to electrons entering the source. Dicklyon (talk) 05:02, 28 March 2012 (UTC)

In explaining the "field that adds carriers to the channel" you had to assume that the source is grounded. This is my point; it's Vgs that mostly matters, in terms of getting electrons into the channel. Suppose you've got source and body at ground, and gate at just below threshold, so you have little or no inversion later, not much charge getting into the channel. Can you then increase the conductivity by increasing the "voltage drop between the oxide-insulated gate electrode and its substrate" by lower the substrate to a negative voltage? No, you can't; that will increase Vth and turn the device more OFF. The idea the the "voltage drop between the oxide-insulated gate electrode and its substrate" is what makes the channel conduct fails, goes in the wrong direction, if what you're moving is the body relative to the other terminals. On the other hand, if you increase the "voltage drop between the oxide-insulated gate electrode and its substrate" by raising the gate potential, you do increase the current; but it's mostly because you increased Vgs. Or at least the usual way of thinking about Vgs seems more consistent than thinking of Vgb as the controlling item. Of course, you need enough Vgb to get a depletion region, or the electrons from the source won't find a suitable place to go. But you need the source to supply the electrons, or you're not going to get a channel, unlike in a MOS cap, where there's no drain to suck off the carriers that are thermally generated. Dicklyon (talk) 05:15, 28 March 2012 (UTC)
 * Hi Dick: Let me repeat a few of your remarks and respond to them.
 * "The part of what you're saying that still confuses me is about what happens when the source and drain voltage are too high, so they take charge out of the channel, but don't put it in. Then the slow carrier generation will never make much of a channel, as the charges will exit as quickly as they are generated; inversion won't happen, even though the surface potential would happily accommodate carriers there, and the voltage that you think of as producing a conductive channel won't do so.
 * These remarks are incorrect. You are imagining a transient situation where equilibrium demands a channel that has not formed. The situation to imagine instead is a steady-state with a channel maintained by communication with the source and drain, and the degree of occupancy available set by Vgb bending of the conduction band. I have added a diagram to show this situation. Brews ohare (talk) 17:22, 28 March 2012 (UTC)
 * "Can you then increase the conductivity by increasing the "voltage drop between the oxide-insulated gate electrode and its substrate" by lower the substrate to a negative voltage? No, you can't; that will increase Vth and turn the device more OFF.  The idea the the "voltage drop between the oxide-insulated gate electrode and its substrate" is what makes the channel conduct fails, goes in the wrong direction"
 * Reverse biasing the source and drain does decrease the channel strength. That does not lead to your conclusion, however. For example, suppose that Vsb is present and Vgb is low. There is no channel. If now we increase Vgb at some point Vgb introduces a channel. The whole process is exactly the same as with Vsb=0, with the change that the Fermi level for occupancy of the conduction band is reduced by the Vsb of the source. So more Vgb is needed to bring the conduction band down close enough to the Fermi level set by the source, close enough for the conduction band to populate near the interface.
 * The mechanism of channel formation due to Vgb does not imply that increasing Vgb=Vgs+Vsb by reverse biasing the body and making Vsb >0 increases the channel strength. It means only what you said first, that Vsb increases the threshold voltage at which Vgb causes the channel to form. You have to bear in mind that a steady-state situation is in mind, not a transient one.
 * It seems as though you insist upon a pure electric field concept of Vgb, and insist upon ignoring the Vsb effect upon populating the channel effected by the change in Fermi level due to Vsb.
 * "Even at mid-channel, if the source voltage is too high, you'll get no channel, because all your mobile carriers will get away quickly. Right?  In that sense, the stuff about channel formation and conductivity seems like just a conventional fiction, not very useful to understanding the current in any region other than strong inversion, and even that is determined more by the source than by the voltages that cause "inversion"."
 * You are introducing a non-equilibrium argument here by suggesting "quickly" has something to do with it. It doesn't. If Vsb reverse biases sufficiently, the channel is extinguished. The Fermi level is lowered. If now Vgb is increased sufficiently, the channel will reform. Carriers in the channel can move freely between source and channel in the final time-independent situation: the definition of Fermi level implies that the same work is done in removing a carrier from the channel as removing one from the source.
 * "I was never in the habit of paying attention to that conventional fiction, since I was working in weak inversion"
 * The description of MOSFET operation provided by text books applies to all operating regimes, including weak inversion. It won't do to describe this accepted analysis as a "conventional fiction". It is mathematically formulated and as accurate as knowledge of the doping distribution in the MOSFET allows. The concepts of strong and weak inversion and deep depletion all are introduced using the MOS capacitor, and they carry over to the MOSFET. The only change in the MOSFET is the ability to change the channel Fermi level using the source and drain contacts.
 * "In explaining the "field that adds carriers to the channel" you had to assume that the source is grounded. This is my point; it's Vgs that mostly matters, in terms of getting electrons into the channel."
 * That assumption is to provide a simple example. As pointed out above, Vgb creates the channel when Vsb is present, but it requires a large Vgb to bring the conduction band down to the Fermi level lowered by Vsb.
 * Dick, short of writing out the 1D Poisson equation with the Vsb Fermi-level effects in the minority carrier charge density and solving them, I don't see how any scheme of words will work. Of course, you may still insist that the equations, which are the same as the MOS capacitor equations, but with the added Vsb effect on Fermi level, are inapplicable, or a conventional fiction, or better described in terms of Vgs instead of Vgb. However one arrives at the 1D Poisson equation, it will prove difficult to explain how Vsb makes it into the 1D Poisson equation without introducing the idea of a change in Fermi level. Brews ohare (talk) 16:07, 28 March 2012 (UTC)


 * Brews, the equations are not at issue, applicability is. The equations assume an equilibrium in which electrons can collect into an inversion region.  I'm just saying that that MOS-cap analysis is not compatible with what happens in a transistor when the source and drain are biased to remove those electrons as fast as they can be provided.  You can still get an equilibrium of sorts, but the generation current will all be coming out the S/D terminals and the amount of inversion charge will be negligible, compared to the MOS-cap equilibrium.  I'm just saying that therefore the MOS-cap analysis is a "convenient fiction" when applied to the transistor, in regions where it is inapplicable.  It becomes more applicable when you discuss the effect of the field in forming a channel as forming a depleted region near the surface that can hold electrons, but then not assuming that those electrons will be there.  That has generally been my attitude toward a "channel": it's a place that electrons can go  through, even if the transistor is turned off due to a too-high source voltage, so there are not currently electrons in there.  In this view, which is more like what we tend to use in subthreshold analysis, where the source boltzmann distribution relative to the channel barrier is key, the Vgb forms a "channel", but doesn't necessarily invert it, and doesn't directly affect "conductivity" in the channel, which is all about how many electrons actually get in there.  As I have pointed out many times, and you haven't objected to, as far as I can see, moving the substrate in the direction that forms more a channel will tend to reduce conductivity, if the source and gate voltages are fixed, and that's why I say focusing on the gate-to-substrate voltage is misleading.  None of the equations are wrong, but you can't understand channel conductivity by paying attention to Vgb and ignoring the source.  Dicklyon (talk) 19:41, 28 March 2012 (UTC)
 * Dick you say:
 * " I'm just saying that that MOS-cap analysis is not compatible with what happens in a transistor when the source and drain are biased to remove those electrons as fast as they can be provided. You can still get an equilibrium of sorts, but the generation current will all be coming out the S/D terminals and the amount of inversion charge will be negligible, compared to the MOS-cap equilibrium."
 * I don't want to offend you, Dick, but this remark is rubbish. The inversion layer is determined as pointed out above, and is not based upon dynamics in which the SRH generation tries to compete with the drain and source sucking carriers out of the channel. The channel population is determined by the usual Boltzmann-Fermi statistics using the modified Fermi level for electrons. Please read over the texts I have suggested to you. Brews ohare (talk) 20:17, 28 March 2012 (UTC)
 * If I'm wrong I'll be happy to be set straight. You're saying that with positive voltages on the source and drain, the charges in the channel won't just diffuse over to and quickly exit to those terminals?  Maybe that's true; I'll have to study up on the situation at the reverse baised junctions, which seem to me would have fields sucking away any electrons that diffuse over near them.   And you still can't just talk about the "conductivity" between S and D, can you, if the current depends so much on the not just the Vds across the channel but also on where the source voltage sits relative to the gate and substrate?  I guess I'm also concerned about the time scale.  If it takes many seconds for thermally-generated carriers to collect to make an equilibrium (like with dark current in an image sensor), then the real operation of the device is going to be mostly determined by non-equilibrium conditions.  Dicklyon (talk) 04:25, 29 March 2012 (UTC)
 * OK, I've reviewed the situation. Everything I see on MOSFETs supports my position that the channel inverts only when Vgs > VT.  That is, no matter what you do with the voltage from gate to bulk, you need to have the gate high enough above the source to get electrons in the channel region.  Are you saying that's not the case, or do we just misunderstand what we were arguing about?  Dicklyon (talk) 05:28, 29 March 2012 (UTC)

Dick: You have not read my explanations in response to your various remarks. Nowhere have I suggested that inversion occurs regardless of the gate voltage. I have said several times and drafted a figure above to show that when Vsb reverse biases the source-to-substrate junction, the necessary gate voltage for inversion increases. The only way I can understand your remark above is that you have read none of these explanations. Nowhere have you addressed the Fermi level splitting caused by Vsb. You have simply slid past this fact. You again raise the issue of time scale, when what is being discussed is a steady-state, not a transient phenomenon. Brews ohare (talk) 14:32, 29 March 2012 (UTC)

And more

 * To the contrary. I have studied your explanation carefully.  I did not mention any concept that is "regardless of the gate voltage".  I'm talking about the effect of the source voltage, in cases where the gate and substrate are fixed to voltages that you say would cause an inversion layer.  Why won't you acknowledge the question?  The question is this: with gate and source high, and substrate low, where do the carriers go that are spontaneously generated?  Do they collect along the oxide interface until you reach an equilibrium like the one in the MOS cap?  Or do they diffuse to source and drain, and exit the transistor?
 * Brews, you've agreed that the MOSFET is a four-terminal device, but everything you say about it is as if the source were always low like the bulk; three-terminal thinking. Why can't you think about the case where the transistor is turned off by raising the source (and drain of course) to above Vg-VT?  Is there a channel in this case or not?  Is it inverted, or not?  In my way of thinking, there's a channel, where electrons would be happy to be, but it's not inverted since any electrons that find themselves there are quickly swept out to S or D by the fields in the depletion regions around those n regions.  In the "conventional fiction" based on only the MOS cap equilibrium, there would be electrons in the channel, and no distinction between channel and inversion.  In a turned-off transistor with high-enough Vgb, these concepts have to be separated; but in most MOSFET descriptions, including everything you've ever written, they remain confused.  Even in ones that are careful to get the channel charge right based on all the voltages, they don't specifically define channel and inversion separately, as fas as I can find, though some avoid inversion as the definition of channel and speak of a "channel region" instead.  Alternatively, some speak of an "inversion layer"  in a non-equilibrium sense as a place that collect electrons, which is how it is used in image sensors .  Dicklyon (talk) 14:41, 29 March 2012 (UTC)


 * Dick, you say:
 * "everything you say about it is as if the source were always low like the bulk; three-terminal thinking. Why can't you think about the case where the transistor is turned off by raising the source (and drain of course) to above Vg-VT?  Is there a channel in this case or not?  Is it inverted, or not?"
 * My discussion covers every possible case. The voltages Vgb and Vsb both play a role. I have taken Vsd=0 for clarity; I don't think Vsd>0 makes any difference to the concepts. I have pointed out that Vsb>0 reverse biases the source-to-substrate junction and this lowers the Fermi level for populating the channel, and for large enough Vsb turns the channel off if Vgb is kept fixed. I believe that is repeated several times above and is the subject of the diagram provided.
 * I don't distinguish between an inversion layer and a channel. The inversion layer provides a conducting path from source to drain, which is the channel. Brews ohare (talk) 17:27, 29 March 2012 (UTC)
 * Nonequilibrium in the sense of transient behavior is not at issue here. Apart from the minor effects of the reverse current drawn through the reverse biased source-to-substrate junction, which makes this technically a steady-state problem, the situation is an equilibrium one, and the equation governing the situation is the standard MOS 1D Poisson equation along a line vertical to the gate extending through the substrate. The minority carrier density is altered by a factor related to Vsb due to the changed Fermi level. Can you address this picture directly? Brews ohare (talk) 17:17, 29 March 2012 (UTC)


 * OK, sorry, I can see that I was in error when I said that I had studied your explanation carefully. There are parts of it that I studied and disagreed with, and parts that are more OK.  But fundamentally, there's still a problem region that the MOS cap approach is avoiding.  Consider the nFET with 2 V threshold, with gate at 5 V, source and drain at 4 V, all relative to a grounded substrate.  Is there charge in the channel, like there would be in a MOS cap with 5 V on it?  No.  If you move the S/D terminal up or down a volt (in the range of 3-5 V, so the transistor stays turned off and the junctions reverse biased), does it affect anything at mid channel?  No, it just affects how much is depleted near those terminals.  If you look at the current into the S+D, do you see the thermally generated current from the whole depletion region (or photocurrent if you shine a light on it), with only a little Vs voltage dependence from the changing depletion region size? Yes.  Do we agree on that much at least?  Do you want to call this steady state an equilibrium, or not?  What do you call the mid-channel state in this case?  Dicklyon (talk) 17:48, 29 March 2012 (UTC)
 * Compare a MOSFET with Vgb=5 Vt=2 Vsb=4 MOSFET to an MOS cap with Vgb=5 Vt=2. Is the same inversion layer present in both? Answer: No. Reason: Vsb lowers the Fermi level and depopulates the channel compared to the MOS capacitor. However, if one uses the MOS capacitor equation and adjusts the minority carrier density according to the Fermi level shift by Vsb, that modified 1D-Poisson analysis governs the MOSFET.
 * Does reverse bias when no channel is present affect midchannel? Answer: Practically speadking, no, but it depends upon what you are looking at. Reason: The situation of a long channel means the reverse bias depletes in a two-D pattern encircling the source. The electron Fermi level in the source and drain is dropped relative to the bulk. What is the Fermi level for the electrons at midchannel? Is it that of the source and drain, or that of the bulk material, or something in between? If the Fermi level for electrons varies with position, a current is drawn. Supposing the midchannel Fermi level is positioned somewhere between the bulk Fermi level and the source Fermi level, electrons will be drawn from midchannel toward the source. For a steady state to prevail a balance is achieved: electrons are drained to the source and supplied by SRH generation in the depletion region. The two balance in steady state, and a steady but extremely small current flows from bulk toward the source. For all practical purposes the slight gradient in Fermi level supporting this minute current toward the source is negligible and we can assume it is vanishingly small. That leads to the traditional approach, the assumption that the Fermi level for electrons across the entire device is set by the source and is flat.
 * Of course, if one were to do an experiment that actually measured the minute electron density at various positions, this approximation would introduce significant error in the electron density. But the electron charge in this situation is not important to device operation.
 * The 1D Poisson at midchannel with no electrons present leads to the same depletion depth as the MOS capacitor with the same gate voltage. That depth is not that of the source-to-body depletion region, of course, and is unaffected by the reverse bias on the source-to-body junction. As the gate bias is increased and the electron density becomes large enough to affect the 1D Poisson equation, the electron density is adequately represented by a Fermi level set by the source, because the miniscule current due to SRH generation still causes a negligible gradient in electron Fermi level. Brews ohare (talk) 18:53, 29 March 2012 (UTC)
 * OK, good, I understand you now, I think. You agree that the source voltage is crucial in determining whether a conductive channel forms, and that the mid-channel is affected by the source in a way that makes the turned-off transistor different from the MOS cap with same gate and bulk voltages in equilibrium.  That takes me back to my original point that the statement in the lead is misleading.  It says:  "a voltage drop between the oxide-insulated gate electrode and its substrate induces a conducting channel between the source and drain contacts via the field effect."  How can this make sense without the source voltage in the picture?  I like how Sze and Ng do it better: "The source contact will be used as a voltage reference... When a sufficiently large positive bias is applied to the gate so that a surface inversion layer (or channel) is formed between the two n+ regions, the source and the drain are then connected through a conducting surface n-channel through which a large current can flow.  The conductance of this channel can be modulated by varying the gate voltage.  The back-surface contact (or substrate contact) can be at the reference voltage or reverse biased; this substrate voltage will also affect the channel conductance."  It's not perfect, but not bad; with the source as reference, the source is playing a primary role; it is, after all, largely what determines the Fermi level that's relevant to channel formation, as you described, and plays a bigger role in modulating conductivity than the bulk does.  That was my original point.  That and the fact the statement we have would suggest a dependence on bulk voltage that goes the wrong direction is everything else is fixed (I realize this is not the intended or correct interpretation, which is why I say it's misleading).  The other thing that's misleading about "a voltage drop between the oxide-insulated gate electrode and its substrate induces a conducting channel between the source and drain contacts via the field effect" and the way such statements and the MOS cap analysis often appear in sources is that they suggest that electrons are "drawn to" the channel, rather mysteriously, without saying where they come from.  In the MOS cap, it can only be by thermal generation.  But in the MOSFET, the affect of those generated carriers is negligible in all regions; when the source and drain are high, they get sucked out with negligible effect, as you describe, and as I kept trying to say without invoking Fermi; and in the ON state they're swamped by electrons from the source.  So the MOS cap provides a good analogy, via the 1D Poisson equation and all, but not an explanation of how the transistor works, which is always much faster than the slow equilibrating of the MOS cap.  Dicklyon (talk) 02:58, 30 March 2012 (UTC)
 * So I changed it to say "a voltage drop across the oxide induces a conducting channel between the source and drain contacts via the field effect." This "voltage drop across the oxide" seems to agree with all that you have been saying, and removes the part that I found misleading, by getting the substrate out of the picture, when the oxide field really just depends on the surface potential, which is affected by a combination of things.  OK?  Dicklyon (talk) 03:32, 30 March 2012 (UTC)

Dick I have no objection to the change to "oxide field". I don't agree with much else that you have said, but this form of words doesn't illuminate our differences, so it is fine. A peculiarity of your description is the emphasis upon the source as having a "bigger role" when both the source and the gate have equally important roles to play. I don't share your view that MOS cap analysis has a mysterious aspect in drawing carriers into the channel, nor your description in the MOSFET of the source and drain sucking out carriers. The whole matter is subsumed by a simple statistical description of the equilibrium population of available energy levels by the Fermi function as set by the Fermi level. There is no need to draw carriers in or to suck them out. There is no dynamical aspect. Brews ohare (talk) 04:20, 30 March 2012 (UTC)
 * I'm saying the role of the source is greater than that of the bulk, not greater than that of the gate. And it's OK that you prefer the statistical view over looking at where the charge is moving. In the transistor, to me it seems that where it's moving is pretty important, and that's often made mysterious by focusing only on the statistical view.  If you don't recognize that thermally generated charges are exiting at the source and drain rather than collecting under the oxide when the source voltage is high, then it's harder to understand where they are or where they go.  You did finally convince me by talking about that that it's not inconsistent with the statistical view, as long as you modify the MOS cap analysis to have a different surface potential set by the source.  Dicklyon (talk) 05:35, 30 March 2012 (UTC)
 * OK, Dick. Just to nit pick a bit, it is voltage differences that control the device, so it is Vgb, and Vsb. (i'm taking Vds=0 for the moment.) When Vsb=0, Vgb can form a channel. When Vgb=0, Vsb cannot form a channel. So one might argue over which is more "important". IMO the easiest perspective is that Vgb positions the energy levels (the conduction band) while Vsb positions the Fermi level deciding occupancy of these levels. What do you thinki about that? Brews ohare (talk) 15:46, 30 March 2012 (UTC)
 * I added a sentence to the body-effect section like this. Brews ohare (talk) 17:14, 30 March 2012 (UTC)
 * Yes, that sounds like a clear way to put it. Dicklyon (talk) 17:40, 30 March 2012 (UTC)

Subthreshold equations
I have an issue that the subthreshold equations are simply incorrect. Yes, the equations are taken from Gray and Meyer, but they are incorrect in the text book. The body effect is required and the "n" that is used as a quality factor is just in appropriate. Kappa would be better. And assuming that the Early voltage is infinite, you get the following through the EKV model: \begin{eqnarray} {\kappa}\;=\;\frac{C_{ox}}{C_{ox}+C_{dep}}, \label{eqn:kappacharge} \end{eqnarray} \begin{eqnarray} I _{nFET}&=& I_{f} -I_{r}, \label{eqn:ekvforbackalpha} \end{eqnarray} \begin{eqnarray} I_{f,r} = \frac{W}{L}2 U_{T}^2\frac{\mu C_{ox}}{ \kappa}\ln^2 \left[1 + e^{\frac{\kappa\left(V_g-V_{T0}\right) - V_{s,d}}{2 U_{T}}} \right], \label{eqn:ekvlightnfet} \end{eqnarray} Degs (talk) 19:22, 14 October 2012 (UTC)

The explanation is too difficult for an Wikipedia article
Pictures are missing, all presentation is hold in place by formulas. The entire article flow is hard to grasp for a beginner.


 * This article reconfirms what I knew 30yrs ago; electrical engineers are idiots. The article has degenerated into a competition for maximizing the amount cut+paste from undergraduate text books, and gives the average reader no useful info. Give a simple idea of what a MOSFET is. Some practical values of Vds Vgs Vth, etc., would be useful. Cut+paste of some 2-port equations out of a text book does not help anyone. How to teach the residue theorem to an elec engineer ... baseball bat and cattle prod is the only way.220.244.237.107 (talk) 04:05, 14 October 2013 (UTC)
 * I've added a "tag" to the article noting that it may be too difficult for Wikipedia's main audience to understand. Please note that adding comments on the _bottom_ of talk pages will get them noticed more easily; it is well possible that yours, being buried in scores of other comments, will be overlooked by most editors. --Nczempin (talk) 01:09, 15 October 2013 (UTC)

Big mistake
This statement is not correct: "The MOSFET includes a channel of n-type or p-type semiconductor material (see article on semiconductor devices), and is accordingly called an NMOSFET or a PMOSFET (also commonly nMOS, pMOS)." Actually an NMOS normally has a P-type channel material. The conductivity of NMOS or PMOS is dominated by electron current and hole current respectively, which is the root for theri definition.

Deleted Section
The channel in a MOSFET is connected on each end to source and drain terminals which are oppositely doped in relation to the channel, and highly doped so that they form low-resistance "ohmic contacts" with metal wires. It is well-known among electrical engineers that a p-n junction allows current to flow only in one direction, from p-type semiconductor to n-type. Since the structure of the MOSFET consists of back-to-back, but oppositely directed, p-n junctions, the MOSFET allows no current to pass in the "off" state, in which no voltage is applied to the gate.




 * Shouldn't this depend on enhancement mode or depletion mode? But even for enhancement mode, when it is conducting after inversion

then the channel effectively has the opposite type. Do you count inversion? Gah4 (talk) 20:23, 25 October 2013 (UTC)

Comment
I've overlooked this when doint the split up. The first sentence is somewhat O.K. But there a no pn-junction in the MOSFET conduction path. It's: ohmic contact - n+ - n-channel - n+ - ohmic contact. Some hard work to do here, perhaps a new picture is needed, adding the n-channel zone under the gate. Pjacobi 21:31, 23 Aug 2004 (UTC)


 * The picture is perfect. It illustrates the MOSFET's *construction* and was never meant to show the various depletion, inversion and accumulation layers that form, widen, compress and vanish during its *operation*. It would take four pictures just to explain the MOSFETs most important operating conditions (thermal equilibrium, cut-off, strong inversion, saturation), and more such conditions exist. It is my current belief that Wikipedia entries should be edited in the style of a vivid and concise encyclopedia, but not as exhaustively as if for a comprehensive engineering or physics textbook.


 * Also, two pn-junctions definitely exist. It is precisely the reverse-biased drain junction that prevents current flow in cut-off condition, for instance. The "ohmic contact - n+ - n-channel - n+ - ohmic contact" conduction path suggested above exists in strong inversion exclusively and gets disrupted in saturation although current continues to flow! Kaeslin 17 Sept 2004.


 * Sorry, if I got this wrong, feel free to revert. But isn't the MOSFET typically depicted as a unipolar device, especially in popular presentations, stresseing the difference to the BJT? So that the picture, even when perfectly illustrating the construction may give a false idea of operation to the non-technical reader? Pjacobi 09:47, 17 Sep 2004 (UTC)


 * Yes, the label "unipolar" is sometimes being used since the charge carriers are electrons or holes exclusively (in n- and p-channel devices respectively) as opposed to BJTs where both types of carriers are involved in the same transistor. I might indeed reinclude the figure if I find leisure to do so. Kaeslin 16:00, 20 Sep 2004 (UTC).


 * One thing that is definitly wrong is the remark about the "metallurgical junctions". If they are to be mentioned, they should be properly marked on top of the diffusion regions.--Qdr 16:28, 17 Sep 2004 (UTC)


 * No, the term "metallurgical junction" refers to the borderline between n- and p-doped semiconductor regions. What you want between the diffusion regions and the metal plugs that connect to them are ohmic contacs, not junctions. Kaeslin 16:30, 20 Sep 2004 (UTC).

QFET?
QFET redirects here, but neither that acronym nor the words Quantum Field Effect Transistor appear anywhere on the article... This was clumsy, and really should be corrected by someone who understands what these terms mean (unfortunately I am not one of those people). KDS 4444  Talk   06:25, 26 November 2013 (UTC)

Unlikely values?
The caption under the picture of the two power mosfets in D2PAK says that these devices are capable of dissipating 100 watts. This seems unlikely to me (by an order of magnitude). Is there a citation for this piece of data? — Preceding unsigned comment added by 68.65.89.98 (talk) 20:36, 9 May 2012 (UTC)

I can't read the markings on the device, but there is a similar MOSFET, based on the description, the Fairchild Semiconductor FQB32N12V2. The datasheet can be found here FQB32N12V2 from Digikey. It will breakdown at 120V minimum and can handle 32A continuous at a 25C case temperature. The junction is rated to 175C. The thermal resistance from the Junction-to-Case is 1 C/W. So for every WATT that the FET needs to dissipate, the junction will rise 1 degree Celsius from the temperature of the case, which for the D2 package is the large tab. So, if the tab is held at 25 C, then the FET can handle (175C - 25C)/(1C/W) = 150W. Holding the tab at 25C is difficult, but possible. The FET can actually dissipate 230W, (175C -(-55C))/(1C/W), if the tab is held at -55C, which is the lowest operating temperature of the junction. Dissipating a higher wattage requires that the tab be held below -55C, which would be outside the operating temperature of the device. This will require a special turn-on sequence to ensure the junction starts at -55C and never drops below it.

The Fairchild Semiconductor FDB024N06, has a Junction-to-Case thermal resistance of only 0.38 C/W for the D2-pak, which equates to 395W when the tab is held at 25C. It can dissipate 605W if the tab is held at -55C. Jeffrobins (talk) 07:25, 17 August 2013 (UTC)

Using the phrase "this devices dissipates" is just confusing to lay people. It should be removed, and the maximum voltage and current should be used instead. — Preceding unsigned comment added by 99.3.46.137 (talk) 23:38, 9 November 2013 (UTC)
 * Maximum voltage or current have no meaning for the mos transistor - i.e. you can have a maximum voltage, let's say, of 100V and a maximum current of 10A. But that would not make the device able to dissipate 1000W. The maximum rated current and voltage are not measured in the same operating conditions. The connection between them is the dissipated power - so if the transistor dissipates 10W nad withstdands a voltage of 100V, the current can be only 100mA. If the current is then 10A, the voltage that can be supported by the device without damage is only 1V.95.76.220.229 (talk) 15:09, 26 November 2014 (UTC)Apass
 * Well, maximum voltage rating and maximum current rating are critical in applying a MOSFET, but the product of these ratings greatly exceeds the allowable dissipated power. The power controlled is much greater than the power lost (dissipated) in the device. --Wtshymanski (talk) 16:43, 26 November 2014 (UTC)

Applications?
The intro to this article seems to focus on the solid-state physics of MOSFETS and not so much the applications. As a mechanical/software engineer interfacing with EEs, I came here wondering what a MOSFET is, by which I mean "why use a MOSFET as opposed to other transistors?" I feel like the intro and the article could do with more information on how MOSFETs are used and on why one would use a MOSFET as opposed to other transistors. That is, what is a MOSFET from a systems perspective, as a component. It doesn't help that the name, "metal–oxide–semiconductor field-effect transistor", puts emphasis on what it's made of rather than what it's for. (Contrast that with two common components that turn mechanical signals to electrical signals: single-pole double-throw switches switch, a potentiometer can be use to measure potential (voltage). Contrast those names with a MOSFET: a transistor that uses electric field to control the shape and hence the conductivity of a channel of one type of charge carrier based on the modulation of charge concentration by a metal–oxide–semiconductor capacitance between a body electrode and a gate electrode located above the body and insulated from all other device regions by a gate dielectric layer made of an oxide, such as silicon dioxide. So is a MOSFET just a switch? —Ben FrantzDale (talk) 12:29, 5 November 2014 (UTC)
 * A continuing weakpoint of Wikipedia articles. I've started an "applications" section but it will need more "why" to explain when MOSFETs are used. --Wtshymanski (talk) 21:01, 6 November 2014 (UTC)

In many cases it is difficult to make an article for all readers. In years past, the differences between bipolar transistors, the other type commonly used in digital logic, and MOSFETs were somewhat generally known. TTL, using bipolar transistors, is still around, but the usual CMOS (and previous NMOS and PMOS) use MOSFETs. (Though now it is usual for the gate to also be silicon, so MOS isn't quite right.) Probably there is another place where the engineering details should go. That should also include the difference between NMOS, PMOS, and CMOS, which also isn't applicable here. Gah4 (talk) 01:03, 11 April 2015 (UTC)

Parasitic Diode
No mention is made of the parasitic diode inherent in the MOSFET design. However the diode is often critical in the design consideration. 194.206.34.233 (talk) 08:11, 10 April 2015 (UTC)

Seems to me, as above, that this is an engineering detail. The usual engineering solution is to bias the substrate enough that such diodes are always reverse biased (for PMOS and NMOS). Gah4 (talk) 01:03, 11 April 2015 (UTC)

History
The History section says: " Following the development of clean rooms to reduce contamination to levels never before thought necessary, and of photolithography[31] and the planar process to allow circuits to be made in very few steps, the Si–SiO2 system possessed such technical attractions as low cost of production (on a per circuit basis) and ease of integration." It seems to me that clean rooms, photolithography, and the planar process are also used for bipolar transistors, so this doesn't really explain the advantage of MOS vs. bipolar in ICs. Seems to me that it is the scaling laws of the two that, depending on available technology, make one or the other a better choice. Gah4 (talk) 01:19, 11 April 2015 (UTC)


 * I agree that this paragraph teases us by claiming there are technical advantages of MOS over bipolar, but never tells us what they are.
 * I think this paragraph brings up more questions than it answers.
 * The 7400 series came in both bipolar and MOS variants, and my understanding is that the "ease of integration" was about the same no matter which 7400 series logic family a designer picked.
 * What exactly is the "ease of integration" of Si–SiO2 being compared to? Perhaps gallium arsenide and vacuum tubes?
 * Are there any references that mention the scaling laws for bipolar? Or (even better) a reference that compares the scaling laws for bipolar vs. the scaling laws for MOS?
 * Is there a way to make this more WP:OBVIOUS that the much cleaner clean rooms required for MOS are a disadvantage of MOS vs. bipolar? --DavidCary (talk) 14:01, 22 July 2015 (UTC)


 * Clean room standards are not the same over the history of chipfab! The standards used in the early days of alloy junction transistors were shockingly bad by even 1970s IC fab standards. If you have access to IEEE Spectrum, try to find an article on the history of the 2N3055. That's a good article, particularly on this topic.
 * Clean room standards were pushed higher by two factors: structure size on the mask (ie LSI) and also by process: thin surface layers for MOS are fantastically fragile to contamination, compared to the robustness of features made by diffusion and placed below the wafer surface.
 * As to ease of integration, then even 74xx00 doesn't integrate well across its technology ranges. You can't mix 74 / 74L / 74H / 74S / 74LS / 74ALS / 74HC without very careful thought, and often only in one direction (The only hands-on I have with 74H was in early-'80s lab exercises to show how hard it was to mix). This is why series like 74HCT had to be invented.
 * I think it's wrong though to suggest that clean room standards are a disadvantage. That's like claiming that TTL is no use over valves because it stops the village blacksmith working on it. Andy Dingley (talk) 14:36, 22 July 2015 (UTC)

Error in the table: Comparison of n- and p-type MOSFETs
Heading for middle column and right column are reversed. The middle column is PMOS, and right column is NMOS. 68.231.211.25 (talk) 14:46, 10 May 2015 (UTC) Tanaka


 * At first glance, it appears to be (mostly) correct. I think the substrate type for a pMOSTFET is wrong.  Rwessel (talk) 18:38, 10 May 2015 (UTC)

As far as I know, the column headings are right, but some others look wrong. One I think is wrong is "channel type". It is usual to describe a FET in terms of its channel type, where nMOS is short for n-channel MOS, but the channel type is when it is conducting. That is, with the inversion layer for enhancement mode. As someone else noted, the substrate type should be changed. Gah4 (talk) 20:12, 19 August 2015 (UTC)


 * I've gone ahead and changed the substrate for pMOSFETs, but I'm not sure about the rest. Rwessel (talk) 04:11, 20 August 2015 (UTC)

External links modified
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Electron mobility?
(below moved to new section, was added to inappropriate section Rwessel (talk) 18:22, 1 November 2015 (UTC))

M S DIVEKAR (talk) 15:31, 1 November 2015 (UTC) I have noticed in equation

ID = μn *COX *(W/L)* ((VGS- Vth)* VDS- VDS2/2)

μn is mobility expressed as cm^2/volt sec.

COX is capacitance per unit area or Farads / cm^2

W is stated to be gate width. Here is a catch. This is a 2 dimensional model and hence I suppose gate width is as per figure below in say cm. As per my understanding W is channel width under the gate. This width is not constant and depends on many factors like applied gate voltage, relative permittivity of oxide and silicon layer as well as conductivity, current carried between the source and drain etc etc. Do note this is enhancement mode MOSFET and W is indication of strength of enhancement in Y axis and not in Z axis. Without a proper figure to clarify, there is scope for misinterpretation.

https://www.dropbox.com/s/i9ha0zkpm0vupuy/Wclar.JPG?dl=0

L is channel length or distance between source and drain in cm.

Further V = Q/C for any capacitor. Hence Q = VC.

So analyzing the equation stated by you time component is missing and there is a dimensional imbalance between left hand side and right hand side. ID is current and mobility term contains a time component in the denominator. So it is not ID but Qsec. This leaves scope for designer to get higher Q at lower Sec or higher frequency component. Thus operating frequency comes into picture. This issue has to be brought out clearly

M S DIVEKAR (talk) 15:31, 1 November 2015 (UTC)