Talk:Metastability (electronics)

Asynchronous circuits and metastability
Moved discussion of asynchronous circuits and metastability to Arbiter (electronics).--Carl Hewitt 21:37, 3 October 2005 (UTC)

NPOV-ish
The last paragraph could use a slightly more neutral tone of voice, but it can wait until there's some additional appropriate content to add there. The concerns expressed are valid; the voice used is somewhat less appropriate.

The issue is NOT peculiar to electronic devices
Any multistable device or system can show similar characteristics. —Preceding unsigned comment added by 174.26.54.150 (talk) 04:47, 21 September 2010 (UTC)

Missing information
I think this article is missing examples and figures to illustrate (it is all text at the moment). At the end it also refers to links; I think it should instead include that informaion.

--Mortense (talk) 06:59, 23 October 2010 (UTC)

The example supplied is precisely the simplest example of what the issue of metastability in electronics is about.
[[File:SRLatch-lowres.gif|thumbnail|An animated SR latch. Black and white mean logical '1' and '0', respectively.

(A) S = 1, R = 0: set

(B) S = 0, R = 0: hold

(C) S = 0, R = 1: reset

(D) S = 1, R = 1: not allowed

The restricted combination (D) leads to an unstable state.]]

The information is certainly not inaccurate and the GIF was simply copied from the flip-flop (electronics) page.

That it is summarily deleted without justification is contrary to multiple principles of Wikipedia. 96.237.136.210 (talk) 05:18, 2 January 2017 (UTC)


 * The figure seems to portray the D case as oscillatory. This is not what metastable usually corresponds to.  In the metastable state, the outputs cannot be interpreted as discreet logical states. Dicklyon (talk) 05:44, 2 January 2017 (UTC)


 * No Dick. This is precisely what the concept of metastability in electronic circuits is about.  And it is the simplest manifestation of the concept that I can think of.  If you can find a simpler example or a better GIF, go for it. 96.237.136.210 (talk) 06:01, 2 January 2017 (UTC)


 * That's oversimplified, so I can't find simpler; nor an appropriate animated gif. But I suggest you have a look at this memoir and Figure 3 in this paper to get an idea how the relevant behavior is not digital.  Portions of these are reproduced in my book chapter. Dicklyon (talk) 06:14, 2 January 2017 (UTC)


 * No, it's not oversimplified, it's the core simplification for an introduction to the concept. I only took a quick glance at the two references you made (which appear pretty old and I don't see why this author is decidedly the authority).  The textbooks disagree with you.  If you Google "digital logic metastability", the first hit is this article.  Then check out the second and the third and the fourth hits.  I am not going to bother scanning the page out of my Roth textbook from the seventies.  I see that there is a (probably not legal) copy of that classic digital logic text online.  Download it and read it.  It's quite fundamental and it was the choice of intro to logic classes I have seen at four different universities as either student or faculty.  Here is another reference that you can download.
 * The metastability of an RS flipflop occurs when both "Set" and "Reset" are asserted, which is a contradictory assertion. But even if it's logically a contradictory assertion (which is why sometimes they say "not allowed"), there is nothing stopping the EE from applying that signal pair to the flipflop.  The result is that the flip-flop is in a metastable state and this is the simplest example that exists for that concept.  96.237.136.210 (talk) 06:49, 2 January 2017 (UTC)
 * There's nothing undefined or disallowed about applying 1s to both NOR gate inputs. The metastability results if those inputs both change to 0s at about the same time.  And the result, as shown by the refs, might be either oscillatory or not, but is not an oscillation between logic states, but rather an electrically undecided state.  If you have old textbooks (70s), they won't acknowledge this, because Chaney and Molnar hadn't yet characterized and published on it (I can't get your Roth textbook to download). And did you know you could give links to your Google hits, in case mine are not in the same order?  Dicklyon (talk) 07:02, 2 January 2017 (UTC)
 * OK, got the Roth book to download; but it's not an old one. It says, "Theoretically, the two-inverter circuit of Figure 11-2 and the set-reset of Figure 11-3 can exist in a third stable state. This is the situation where the voltage level at the output of the two inverters or gates is approximately halfway between the voltage levels for a logic 0 and a logic 1. This state is referred to as a metastable state."  Obviously this is unlike your simplification to logic state oscillation. Dicklyon (talk) 07:22, 2 January 2017 (UTC)
 * Also, if you don't see why Tom Chaney and Charlie Molnar and Fred Rosenberger are the authorities, you're not really up on this concept at all. Go study their papers.  Or give Tom a call. Dicklyon (talk) 07:30, 2 January 2017 (UTC)

[[File:SRLatch-lowres.gif|thumbnail|An animated SR latch. Black and white mean logical '1' and '0', respectively.

(A) S = 1, R = 0: set

(B) S = 0, R = 0: hold

(C) S = 0, R = 1: reset

(D) S = 1, R = 1: both outputs low

A transition from combination (D) to (B) leads to a metastable state, portrayed here as an oscillation between logic states.]]

For now, I changed the caption. But the figure is still not right, as it shows state (D) as having some funny input values, neither black nor white marbles, rather than showing a transition to input configuration (B) which is what can provoke the instability. Dicklyon (talk) 07:38, 2 January 2017 (UTC)


 * I agree with Dicklyon. Your motive in adding the image was unimpeachable, 96.237.136.210; this article desperately needs some good diagrams.  However the flipflop animation, while an honest attempt to represent metastability, is just too misleading and will give introductory readers an erroneous impression.  The animation doesn't show a metastable state, the only states it shows are logic 1 (black ball) and logic 0 (white ball).  As Dicklyon said, a metastable state is not an oscillation between stable states, it is an intermediate value.  -- Chetvorno TALK 08:39, 2 January 2017 (UTC)

That's not metastability that's being shown, although metastability might occur when you remove the two one RS inputs.

Maybe we could get some informative graphs out of a transistor level LTSPICE simulation or something.GliderMaven (talk) 16:45, 2 January 2017 (UTC)
 * Exactly; if you vary the timing of the transitions from 1 to 0, you can plot a range of responses and demonstrate a few that take a long time to resolve; like in the oscillogram in the Chaney and Molnar paper that I linked. SPICE should be up to it if someone wants to give it a try. Dicklyon (talk) 17:46, 2 January 2017 (UTC)

I agree with the IP that the SR NOR latch is a good simple example, so I edited and expanded on that part of the contribution, and included a simple static schematic. Dicklyon (talk) 21:18, 2 January 2017 (UTC)

Exponential decay
The article currently states:
 * ... a bistable device can enter into a state that is neither true nor false and has a positive probability that it will remain indefinite for any given period of time, albeit with exponentially decreasing probability over time.

but this seems dubious to me. It makes as a base assumption that the decay is exponential. Yes, the exponential has infinite support (mathematics) so if its actually exponential, then the statement is true. But exponential assumes that the equation describing the system is a simple first order ODE; for more complex PDE's, its not obvious that the solution wouldn't have finite support (i.e. the probability shrinks to exactly zero in finite time.) Examples of such equations are things that have a topological soliton, e.g. the KdV equation, but also e.g. things with lax pairs, etc. (basically, you need to cook up a diff eq that has a textbook bump function as a solution, and bingo, indeterminism is bounded, right?) I'm objecting to the idea that the indeterminism is necessarily unbounded; it is not obviously so. 67.198.37.16 (talk) 07:50, 20 January 2017 (UTC)


 * I think you're mistaken. First, the response doesn't need to be exponential for the probability of still being indeterminate after a time to be exponential.  You can get this with a system of any order, or a PDE, that has a metastable point in its state space.  If it's possible to cook up equations that don't behave this way, I don't understand how. Dicklyon (talk) 07:58, 20 January 2017 (UTC)