Talk:Multiple-emitter transistor

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Is a multiple-emitter transistor exactly equivalent to a pair of transistors with common collectors and common bases? — Preceding unsigned comment added by 87.194.171.29 (talk) 11:32, 18 April 2011 (UTC)

The latest change was just counterproductive

 * https://en.wikipedia.org/w/index.php?title=Multiple-emitter_transistor&diff=889052813&oldid=888982006

I didn't clarify the AND/NAND issue because I insist on either variant, but because the logic input patterns in all versions before were plain wrong in regard to the purported outputs:

First it was


 * "Collector current stops flowing only if all emitters are driven by the Logical high voltage, thus performing an AND logical operation using a single transistor",

then


 * "Collector current stops flowing only if all emitters are driven by the logical high voltage, thus performing a NAND logical operation using a single transistor",

and finally


 * "Collector current stops flowing only if all emitters are driven by the logical low voltage, thus performing a NAND logical operation using a single transistor"

Since collector current only starts flowing, if all emitters are driven by logical high voltage, and stops flowing in all other cases, the article had been factually wrong for 10 years straight, until I fixed it a few hours ago. Then (and only then) you come running, Dicklyon, and remove references to gate logic altogether to reduce the amount of information in the stub even more. This really isn't helping at all.

Furthermore, your comment


 * "saying what kind of gate it is depends on how voltages and currents are associated with logic values; no need to argue about that"

is inapplicable, because we are mostly talking about TTL NAND gates here, at least that's what the article says.

TTL standard of course still is an input signal between 0 and 0.8 V as a logical 0 as well as between 2 and 5 V as a logical 1. As I've explained in my edit: "The single transistor function is an AND, the gate overall then becomes a NAND by triggering a second transistor (hence TTL)."

On a sidenote: even if you'd redefine high voltage as logical 0 and low voltage as logical 1, the AND function would still not turn into a NAND, but into an OR instead. Meaning: the alleged "argument" and edits of AND vs NAND haven't got anything to do with the logic value association with different voltages.

Last but not least: your edit is simply misleading, because there is no collector current flowing unless all emitter inputs are high.

Please revise or revert. --85.212.186.26 (talk) 12:04, 23 March 2019 (UTC)


 * Many thanks for correcting the factual inaccuracy in this article. My input regarding the article content is that we should take care when discussing "collector current" in the input device of a TTL NAND. One reason is that the only sustained collector current flow is negative in the sense that it exits the collector of the NPN device.  When both emitters are pulled high, the device operates in the reverse-active mode of operation, which is rarely implemented except in this device.  Since the use is obscure, any discussion of  collector current requires care to be both factual and intelligible.


 * Another reason to be careful when discussing this collector current has to do with the reason that the current falls to zero. This reason is that the multiple emitter device's collector drives the base of an NPN into the cut-off region. That NPN base is the inverting transistor of the totem pole output, which is not mentioned in this article. If it were not for this unmentioned device, the current would not be zero, in general.


 * If I find the time, I can propose text for the article for people to review. In any event, I would like editors to understand the potential pitfalls of the term "collector current" in this transistor. Thanks again, Overjive (talk) 07:48, 24 March 2019 (UTC)