Talk:Norsk Data Assembler

-- Made a preliminary description of the MAC assembler. Also made a reference to a page describing the ND-100 and relatives' instruction set. This page does not exist yet. I do not have a ND-100 nearby and I cannot remember the opcodes etc for the instructions but it would be nice if someone who does have the proper documentation could add some info about this. The table should detail which processor was the first to include the instruction etc. Also perhaps have a table of SINTRAN III monitor calls and which version of SINTRAN included that call.

Just to list some of the instructions that I remember - it is 20 years since I programmed on it so bear with me if it is rusty.

First a little about memory addresses:

Anywhere where I below write addr, I mean the address computed. This was typically in the form of an 8 bit offset modified by 3 bits X, I and B. If X bit was set you added in the X register, if the B bit was set you added in the B register and if the I bit was set, the address was the location of a pointer pointing to the location you wanted. Note that if all of X I and B was set the B register was added to the offset and then an indirection was done and then the X register was added to the contents at B + offset. If neither X nor B was specified, the computer used P-relative addressing where the effective address was P + offset.

If I below write addr without [], it means use this address instead of fetching data from the address.

Arithemtic and logic:

ADD addr ; A := A + [addr] ADX addr ; X := X + [addr] SUB addr ; A := A - [addr] SBX addr ; X := X - [addr] MUL addr ; D := high part of A * [addr], A := low part DIV addr ; D := remainder of D:A / [addr], A := quotient ORA addr ; A := A OR {addr] AND addr ; A := A AND [addr] XOR addr ; A := A XOR [addr]

Control instructions:

JMP addr ; P := addr JAZ addr ; if A == 0 then P := addr JAF addr ; if A != 0 then P := addr (jump if A is filled) JXZ addr ; if X == 0 then P := addr JAN addr ; if A < 0 then P := addr (jump if A is negative) JAP addr ; if A >= 0 then P :+ addr (jump if A is positive)

Loading and storing data:

LDA addr ; A := [addr] LDX addr ; X := [addr] LDT addr ; T := [addr] LDD addr ; D := [addr]; A := [addr+1] STA addr ; [addr] := A STX addr ; [addr] := X STT addr ; [addr] := T STD addr ; [addr] := D; [addr+1] := A

MIN addr ; [addr] := [addr] + 1; if [addr] == 0 then P := P + 1
 * some miscallaneous memory instructions


 * Register instructions.

COPY Sr1 Dr2 ; reg2 := reg1. note that the sequence of the registers doesn't matter. COPY SA DT is exactly the same instruction as COPY DT SA. Both copy A over to T. T := A.

RADD Sr1 Dr2 ; reg2 := reg1 + reg2 You could add options to this operation such as ADC to add carry and AD1 to add 1. Another option CM1 complemented reg1.

RSUB Sr1 Dr2 ; reg2 := reg2 - reg1. This is actually RADD CM1 AD1 Sr1 Dr2 (complement and add1 to source register).

SWAP Sr1 Dr2 ; temp := reg2; reg2 := reg1; reg1 := temp

RAND Sr1 Dr2 ; reg2 := reg2 AND reg1 ROR Sr1 Dr2 ; reg2 := reg2 OR reg1 RXOR SR1 Dr2 ; reg2 := reg2 XOR reg1

There was also shift and rotate instructions but I can no longer remember the details of them. I just remember that you had options there to specify to use the L bit in status register as the bit to fill in as new bit. So if you shifted left 1 bit so bit 15 was "lost" (actually copied to the L bit), bit 14 was copied to bit 15 etc and bit 0 was copied to bit 1 and then original L bit was copied into bit 0 when this option was on. Otherwise it would copy 0 into bit 0 (bit 15 would still be copied to L bit).

The MON instruction was similar to the intel processor INT instruction and generated an interrupt that trasnferred control to the interrupt level that was enabled for this interrupt. When SINTRAN was running that was level 3. This means that it was the P register of level 3 that determined the next instruction to execute. Further, the operand could be retrieved and used as index in a jump table that processed the interrupt.

There was also a host of special instructions such as POF to turn off paging, PON to turn on paging. An instruction to execute the contents of a register as an instruction, instructions to read and write to physical memory (bypass memory address translation) and of course input output instructions: IOX. I would appreciate it if anyone can provide more info about these details.

salte 16:27, 8 December 2006 (UTC)


 * To the above I can add:


 * STD and LDD instructions had the registers the other way around, i.e.

STD addr ; [addr] := A; [addr+1] := D LDD addr ; A := [addr]; D := [addr+1]


 * The one-bit accumulator was kalled the K bit, not the L bit.
 * TArntsen (talk) 08:24, 30 July 2009 (UTC)
 * Correcting myself, the one-bit accumulator was indeed the K bit, but the bit in the status register that was used as a stepping stone in shift operations called M, not L, but the full name was "Multi-shift Link indicator" so that's presumably where the "L" in the discussion above came from.TArntsen (talk) 09:41, 30 July 2009 (UTC)