Talk:Northbridge (computing)

Dummy?
Why is this article so desperately dummy? Looks like people writing it have absolutely no knowledge about hardware design or BSP writing, and just know about overclocking or read vendor marketing literature. If the math articles on Wikipedia were written from the same point of view, they would talk about selecting the best looking fonts for writing formulas...
 * They were waiting for you to come and improve the article, but it seems like criticising in the only thing you can do ? &rarr; SeeSchlo&szlig; 2 July 2005 14:16 (UTC)
 * Right, Matthieu. What this article needs is another contribution from an "almost-competent" person. Avoid repeating pre-packaged wit & wisdom, take a clue, maybe look at "PCI express" or even "Southbridge" articles.
 * Heh, since you seem to know better than the previous contributors, I was (am) just wondering why you don't improve it yourself. I'd do it if I knew anything about northbridges but I don't. &rarr; SeeSchlo&szlig; 2 July 2005 21:25 (UTC)

what is a "die"?
"Rarely, these two chips have been combined onto one die when design complexity and fabrication processes permit it."

That says a lot but I do not know what a "Die" because it is not hyperlinked.
 * I don't know how to exactly use wikipedia, but a Die is a chip pretty much. That is saying pretty much, "Rarely, these two chips have been combined onto one" chip "when design complexity and fabrication processes permit it."
 * fixed. can we remove this section? Cesium62 23:27, 20 August 2007 (UTC)

ANSWER: A die can be defined as: an engraved stamp for impressing a design upon some softer material, as in coining money. That means that the two chips are nowadays combined and they are seen as one. Similar to the L2 cache combined to the CPU
 * "A die can be defined as: an engraved stamp for impressing a design upon some softer material" <-- that is not what die means in this context. Die in the context of electronics refers to the raw silicon chip which is then mounted in a package or occasionally direct to the PCB. Usually there is one die per package but sometimes there are more (e.g. the pentium pro, the pentium D, the core 2 quad and several other intel processors) 86.1.116.158 (talk) 01:30, 18 December 2009 (UTC)


 * It turns out that even back when this question was asked that the Die (integrated circuit) article was available. --Marc Kupper&#124;talk 06:07, 15 March 2024 (UTC)

Confusion
The southbridge article claims that PCI Express is handled by the shouthbridge, and this article claims that it is the northbridge. Which is it?


 * The Northbridge controls PCI Express 16 exclusively for Video. You will never see the South bridge control newer high end Video cards on AGP or PCI-Express 16.


 * The Southbridge may control PCI Express 1, which will be the new standard replacing PCI. This includes a new SoundBlaster in the works and high end Network cards etc.  My motherboard already has PCI-Express 1, which is only 1/4 the sive of PCI-E 16 used for Video cards.  Eventually the old 33Mhz PCI standard will be replaced completely as AGP has been replaced by PCI-E 16.


 * (An answer from someone else)


 * Both. This depends on the chipset. Some chipsets (nForce 4),(AMD 8000) implement all PCI Express links in the northbridge chip. Others (Intel P965) have 16 PCI Express lanes in the northbridge and 6 in the southbridge. Others (Intel 5000) have all PCI express links in the north bridge, but physically route a few through the southbridge chip.
 * In general the northbridge handles faster stuff and the southbridge handles slower stuff, what counts as "faster stuff" and what counts as "slower stuff" changes over time. At one time i'm pretty sure PCI counted as fast stuff and was supported by the northbridge but by modern standards it counts as slow stuff and is pushed off to the southbridge. PCIe supports a wide range of different bandwidths depending on how many lanes are used and as such you usually get some PCIe connections off the northbridge and some off the southbridge (for example the workstation board I just put in an order for has the x16 2.0 slots and the x4 1.x link for the dual gigabit ethernet off the northbridge but the x4 slot, the x1 slot and the x1 link for the onboard graphics off the southbridge. Plugwash (talk) 00:59, 19 December 2009 (UTC)

RAM limit
"...though motherboards that can support that much RAM are rare because of other factors (operating system limitations and expense of RAM)."

What do the OS limitations and expense of RAM have to do with how much RAM a motherboard can support? Can someone please expound? Viper5030 (talk) 21:33, 23 July 2008 (UTC)
 * Market segementation, if you want a LOT of ram they like to force you to expensive server/workstation soloutions. What counts as a lot of ram depends on other factors in the market (price of ram and ram support of the dominant desktop OS Plugwash (talk) 01:33, 18 December 2009 (UTC)

nForce2 Compatibility
Quoted from the article: "For example, the northbridge from the NVIDIA nForce2 chipset will only work with Duron, Athlon, and Athlon XP processors combined with DDR SDRAM,"

It might be worth noting that most, if not all, nForce2-based motherboards also work with Socket A Sempron processors (which are heavily based upon the Athlon XP design), usually requiring only a firmware update for proper detection so they aren't treated as Athlon XPs with an incorrect performance rating, as was the case with my current system. --- Randilyn 21:46, 21 November 2006 (UTC)


 * I believe I have clarified this, please see if it reads alright to you. 70.105.251.33 04:56, 13 July 2007 (UTC)

MCH/GMCH Terminology
The terms MCH and GMCH are attributed to Intel, no other major vendor I know of (Via, Nvidia, SiS) uses these terms, and their marketing people would probably get very confused if you asked them about their MCH's. This article is in need of some serious cleanup, as was stated 2 years ago, but I don't have the time to do it. 70.105.251.33 04:49, 13 July 2007 (UTC)

Merger
Since there's no actual discussion about merging the northbridge and southbridge articles and because there's no reason stated as to why the merger should take place, I've decided to remove the merge templates. —Preceding unsigned comment added by Svadhisthana (talk • contribs) 20:49, 13 August 2008 (UTC)

memory controller hub
First sentence: The northbridge, also known as the memory controller hub (MCH) in Intel systems (AMD, VIA, SiS and others usually use 'northbridge'), is traditionally one of the two chips in the core logic chipset on a PC motherboard, the other being the southbridge.

The Northbridge and Southbridge memory controller hub's, are they MMU's (Memory management unit's)? http://en.wikipedia.org/wiki/Memory_Management_Unit —Preceding unsigned comment added by 92.238.93.209 (talk) 10:21, 24 October 2008 (UTC)


 * The northbridge is the device that contains the memory controller. The Memory management unit, or unit(s) which provide the same functionality, are located in the microprocessor in modern designs. Rilak (talk) 08:34, 25 October 2008 (UTC)


 * The MMU is a security module that controls Paging and Segmentation, and lives inside the chip. The Memory Controller is closer to a "latch" (oversimplifying) that connects the address and data bus to the Memory.--BlackLynx (talk) 22:49, 28 January 2009 (UTC)


 * The memory controller is a latch? That is oversimplifying it a bit too much! :) Rilak (talk) 04:13, 31 January 2009 (UTC)

Chipsetfunctions.png
I am a bit confused... does the image imply that the microprocessor is directly connected to the memory and does not access it via the memory controller in the northbridge? Rilak (talk) 11:58, 8 November 2008 (UTC)
 * Yeah... Additionally, since when "Secondary storage" is not part of "I/O"? Confusing. --Kubanczyk (talk) 20:18, 8 November 2008 (UTC)
 * And the northbridge decides what the microprocessor executes? And since when was the BIOS and NVRAM part of the memory? The BIOS and NVRAM are usually on the LPC bus which is connected to the southbridge, with the BIOS stored on the Firmware Hub (in Intel chipsets at least). Is this from a programmer's point of view or from an architectural (and physical) point of view? And what is with the red and blue arrows? Perhaps the image needs to be taken down for revision before it is reinstated? Rilak (talk) 06:25, 9 November 2008 (UTC)

Why is the north bridge so big?
The only explanation I can think of is the #pins is large, hence the large chip, but the circuitry is relatively small. Given that integrated CPU/north bridge chips aren't 2x bigger would mean the northbridge circuitry is small. Anyone know the details? --UncleJoe1985 (talk) 11:10, 1 January 2010 (UTC)

Challenge of information in article
It is time to stop referring to the northbridge as a "chip." With the introduction of "Sandy Bridge" processors, northbridge becomes a function or region of the CPU chip, not a separate chip. This should be acknowledged in the first sentence or else the article should be rewritten as computer history. —Preceding unsigned comment added by 72.65.204.46 (talk) 06:05, 12 January 2011 (UTC)

Under "North Bridge and Overclocking" it states: "AMD CPUs are only limited by physical factors such as thermal instability which causes a fatal system crash, but can theoretically overclock infinitely" This is incorrect as electronic circuits are limited to the propergation delay on the gates that comprise them, there is a maximum rate to which a circuit can be clocked, and then it will become unstable and not operate correctly. For more info see Propagation_delay. I also get the impression the guy who wrote this bit has a bit of a leaning towards AMD as well - why should it be that only be AMD CPU's that can be overclocked infinitely? - Should they actually be able to, which they can't. --144.32.55.159 (talk) 07:41, 12 March 2010 (UTC)

History of the term
It would be nice to say a little bit about when the north/south bridge terminology came into use. When i was a lad, there weren't bridges (in microcomputers - big iron has had more bridges than Königsberg for generations) - the processor talked to the bus, and the bus had various things - memory, IO, graphics controller, whatever - hooked into it. The fragmentation of the single system bus into a bus hierarchy - first memory vs IO, then memory vs faster stuff vs slower stuff, the proliferation of sub-buses like USB and SCSI - came later. The idea of these two bridge controllers can only have emerged once that fragmentation was well underway. When did that fragmentation happen? When did the two controllers take their places? When did the terminology come into use? — Preceding unsigned comment added by 109.231.204.82 (talk) 19:16, 15 July 2011 (UTC)
 * I think the history question is answered on List of Intel chipsets and to a lesser extent on List of AMD chipsets. Those articles don't seem to answer when the chipsets started to get called the northbridge and southbridge.


 * Some of what you called "fragmentation" goes back to the earliest computers where the details of tasks, such as printers, tape, disk control would get offloaded to separate boards. Even in the 1950s and certainly by the early 1960s many controllers had their own CPUs or sets of chips that acted like a CPU. A computer "system" has many busses and interconnects.


 * As the density of integrated circuit chips increased it became possible to bundle common sets of discrete chips and components within a single chip or set of chips. The trend continues today.


 * Unfortunately, none of this seems to help answer the question of when chip sets started getting called "northbridge" and "southbridge." Once of the things Intel does to promote sales of their own parts is to offer reference designs. I suspect someone could dig through the the archived reference designs to see when they started using the "northbridge" and "southbridge" terms. --Marc Kupper&#124;talk 04:52, 15 March 2024 (UTC)

Graphics integrated into northbridge
from what I heard, the 2009 macbook air has the geforce 320m integrated onto the northbridge, though I couldn't manage to find full details on it. Can someone confirm? Also, can put that into the page? 175.156.209.60 (talk) 14:09, 13 August 2011 (UTC)
 * A chip soldered onto the motherboard is not the same as integrated into the northbridge. --Denniss (talk) 15:45, 13 August 2011 (UTC)

Seems that for the macbook air 2010, the GPU, southbridge and northbridge are integrated into a single package. ifixit picture: http://guide-images.ifixit.net/igi/4uUMRIPytboUt2Ti.large I'll go find some references and probably update the page? 175.156.215.250 (talk) 06:42, 14 August 2011 (UTC)

"the 320M northbridge/southbridge/GPU combo chip" http://digitalgravitas.wordpress.com/2010/10/25/the-macbook-air-a-sign-of-things-to-come/ 175.156.215.250 (talk) 07:54, 14 August 2011 (UTC)

Link rot
In very first of the references, TechTarget no longer has the Southbridge defn page (a Wayback capture is at https://web.archive.org/web/20211028213303/http://whatis.techtarget.com/definition/Southbridge) and IAC the content isn't very consequential/essential to this article. — Preceding unsigned comment added by 96.78.143.225 (talk) 05:06, 14 May 2023 (UTC)