Talk:OpenRISC 1200

Performance
I'm not sure the performance figures are at all helpful, and in the absence of a citation, I find them very hard to believe. The OpenRISC typically runs on FPGA's clocked at 25-50MHz, although the latest FPGAs can wind that up closer to 100MHz. There are known issues with the implementation of the caches and MMUs that constrain performance. Jeremybennett (talk) 19:53, 24 October 2011 (UTC)
 * Following discussion with various OpenCores contributors, no one seems to believe these are credible performance data. In the absence of a citation, I propose removing them (and possibly replacing them with substantiated data). Jeremybennett (talk) 20:08, 24 October 2011 (UTC)
 * I've added CoreMark information, which is more useful compared to the often-inflated Dhrystone MIPS numbers that get bandied about. Juliusbaxter (talk) 20:41, 24 October 2011 (UTC)

The statement "1W at full throttle and less than 5mW at half throttle" lacks plausibility. 2.246.74.215 (talk) 15:21, 30 May 2015 (UTC)

History
The history section was wrong, reflecting a confusion between the OpenRISC 1000 (which is an architectural specification for a family of processors) and the OpenRISC 1200 which was the first implementation of that architecture. Text corrected. Jeremybennett (talk) 19:49, 24 October 2011 (UTC)