Talk:PCI Express/Archive 2017

Clarifications
I read this article and was left puzzled by a couple of things. I'm (obviously) not very knowledgeable about this stuff, but I was left puzzled by the lack of clarity here. One issue is with the PCI Express Link Performance table. The column labeled "Transfer Rate" is really strange. If it is technically correct, that is, if the terminology is correct (I understand that it is a correct description) it still uses units of GT/s which I've never seen before. Why not use, either as a substitute or in addition to this terminology the far more common AND far more understandable "Clock speed" and GHz ? I think this would make the rest of the table far more understandable. Another issue with the table, specifically footnote i is what it says:"In each direction (each lane is a dual simplex channel)." Which of the editors/authors of this article thinks "dual simplex channel" means anything to 99.5% of the readers? Is it also true that each lane is a paired duplex channel (or something similar)? So, again we have the problem that it lacks clarity. The entire section on Lanes left me scratching my head until I found more information elsewhere. "differential signalling pairs"? What are they? Why are they used? It's simple: Each lane is composed of two pairs of one-way lines, one pair for each direction. Each pair consists of two lines, one line mirroring the other (the other's compliment or opposite). This drastically reduces the electromagnetic noise the signal sends out around itself, and so dramatically reduces transmission errors at today's high speed (MHz, GHz) clock speeds. I think the article would benefit from inclusion and modifications similar to the one's I suggest here. I hope the editors agree, and if not then attempt to clarify the table and the Lane paragraph themselves.98.17.93.163 (talk) 20:07, 8 January 2017 (UTC)


 * GT/s is linked, just read the article – for clarity, that term is best to use here; neither "clock speed" nor GHz would be correct. 'Dual simplex' is linked now (thanks), it's not the same as full duplex. 'Differential signalling' is also linked, just take a read. Diving into telecommunication and information theory wouldn't really help here, there are other, better articles for that. Covering an advanced, high-tech topic from top to bottom is not possible within the scope of a single article imho. --Zac67 (talk) 21:24, 8 January 2017 (UTC)

External links modified
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I have just modified 3 external links on PCI Express. Please take a moment to review my edit. If you have any questions, or need the bot to ignore the links, or the page altogether, please visit this simple FaQ for additional information. I made the following changes:
 * Added archive https://web.archive.org/web/20071208162241/http://www.interfacebus.com/Design_Connector_PCI_Express.html to http://www.interfacebus.com/Design_Connector_PCI_Express.html
 * Added archive https://web.archive.org/web/20100817201815/http://www.eiscat.se/groups/EISCAT_3D_info/DeliverableWP12.2/preview_popup to http://www.eiscat.se/groups/EISCAT_3D_info/DeliverableWP12.2/preview_popup
 * Added archive https://web.archive.org/web/20071208162241/http://www.interfacebus.com/Design_Connector_PCI_Express.html to http://www.interfacebus.com/Design_Connector_PCI_Express.html

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Cheers.— InternetArchiveBot  (Report bug) 15:29, 27 July 2017 (UTC)

PCIe 5.0 is coming with 32 GT/s
Why was my edit reversed?

Source: --  194.0.94.11 (talk) 09:04, 6 September 2017 (UTC)

Source 52 wrong?
Finally announcement of the SIG group was on 5th October: [] --  195.189.94.14 (talk) 12:27, 26 October 2017 (UTC)