Talk:PSE-36

then 4 more bits, in addition to the 10 bits used in PSE, are used
ARE used or MIGHT BE used?


 * On a PSE-36 capable CPU there is no "PSE, but not PSE-36" mode available. So when PSE mode is enabled (CR4 bit 4) bits 16 through 13 of the page directory entry (PDE) are always going to be interpreted by the MMU. If you have an older OS that is only aware of PSE, then it should have always been writing zeroes into those bits all along (because they are described as "must be zero" under PSE non-36), so the OS keeps working just as if it was on a PSE non-36 CPU. If your OS is aware of PSE-36 then your OS can, if there is more than 4 GB RAM, put non-zeroes into those bits and thereby reach addresses above 4 GB. Jeh (talk) 09:42, 29 December 2012 (UTC)

How is PSE-36 mode initialised (like told about CR4 bit 4 of older PSE mode)?


 * The same: by setting bit 4 of CR4. Again, on a PSE-36 capable CPU, there is no "PSE but not PSE-36 mode", so setting this bit enables PSE-36. But as I described above, PSE-36 is completely backwards compatible with OSs that only are aware of the older PSE mode (supporting no more than 32-bit physical addresses) so there is no need for PSE and PSE-36 to be independently controlled. Jeh (talk) 09:42, 29 December 2012 (UTC)

How are PSE and PSE-36 pages told one of another?


 * They're not. There is nothing in the page directory entry that says "PSE-36". On a PSE-36-capable CPU, a PDE that addresses a large page that's under the 4 GB physical address boundary looks exactly like, and behaves exactly like, a PDE on a PSE non-36 CPU. Think about the above two answers and I think you will "see" it. Jeh (talk) 09:42, 29 December 2012 (UTC)

What is a D-bit (bit 6 of page entry) meant for? This bit is highlighted, but not described.


 * It's the "dirty" bit, more nicely thought of as the "page modified bit". It's described in the current version of the article. Jeh (talk) 09:42, 29 December 2012 (UTC)

interwiki
Please don't link this with PAE in other wikis. --a5b (talk) 12:45, 1 October 2009 (UTC)

Is it used?
Is PSE-36 used by any x86 operating system? --RokerHRO (talk) 13:57, 13 September 2010 (UTC)


 * Yes. But it's commonly called "large page" support. Modern Windows versions and most Linux versions use it for something or other although the "ordinary" page management is still done with small pages. In Windows 7, large pages are used to map a few large modules such as ntoskrnl.exe, certain kernel-space allocations use large pages (commonly used for DMA "bounce buffers" and similar), and applications can even ask for large pages on VirtualAlloc calls. I can't provide *nix details. Jeh (talk) 02:01, 29 December 2012 (UTC)
 * You are confusing it with plain PSE. Someone not using his real name (talk) 23:15, 1 March 2014 (UTC)
 * No, I'm not. The mechanisms I described use PSE-whatever, where -whatever is the number of physical address bits that can be provided for a large page by address translation on the local processor. On a processor that implements PSE-36 (and an OS version that supports using more than 4 GB RAM) then such allocations can end up using physical pages above the 4 GB boundary, but that is more or less incidental. The claims in this article that PSE-36 is not used for much of anything on Windows are wrong. Even NT4 used PSE (not -36 of course) to map ntoskrnl.exe... but really, drawing such a distinction between PSE and PSE-36 is misleading. Windows 2000 also used it to map ntoskrnl.exe and was not limited to PSE-not-36, not on the higher end server SKUs anyway. Jeh (talk) 02:43, 3 March 2014 (UTC)


 * Oohhhhh, I see. PSE-36 refers specfically to the trick of burying four more bits of RAM address in the PDE, using some of the bits that would ordinarily "MBZ" under plain PSE. Got it. Jeh (talk) 03:28, 3 March 2014 (UTC)

Which processors?
The article says when PSE-36 appeared. Did they drop it or is it in all subsequent processors? Core 2 Duo reports "pse", "pse36", and "pae". --A876 (talk) 20:13, 28 December 2012 (UTC)


 * No, it's still there (and is used by modern OSs; see above) though I wouldn't be quick to say "all subsequent processors." For example, it's possible that low-end stuff like the Atoms didn't implement it. Jeh (talk) 02:03, 29 December 2012 (UTC)
 * I don't think any modern OS uses this. Even Windows stopped using it in favor of PAE starting with Windows 2000. Linux never used it. See refs in article. Someone not using his real name (talk) 23:13, 1 March 2014 (UTC)

Intel "PSE-40"
Shanley, in his 2009 book, says that "Intel followed suit" by also implementing this obscure extension. I haven't seen it in Intel's manuals yet. Someone not using his real name (talk) 02:44, 2 March 2014 (UTC)
 * Ok, I found it. It's in some almost-lawyerese text. Basically it's between 36 and 40. A google search for "CPUID Maximum Physical Address Bits supported across all CPUs" will find some interesting values for Intel CPUs, typically 36, but 38 or 39 bits can also be found. Sandy Bridge EP has 46 though (so it would support PSE-40 in full, assuming you could plug 1TB of RAM on typical EP MB). Someone not using his real name (talk) 03:38, 2 March 2014 (UTC)
 * Even more strangely, some AMD CPUs return less than 36 (but more than 32) bits for this, e.g. 34. Someone not using his real name (talk) 03:52, 2 March 2014 (UTC)