Talk:Phase detector

Untitled
a signal changes its phase by 2 pi multiplied its frequency. phase detector can be realised by sequencial as well as analog circuit by didode or cmos for high speed. normally a charge pump is required before filtering the dc ouput by low pass filter, a charge pump gives constant current output which is nothing but a three pole switch. many software is availave for pll simulation from which code loader is the modarate freeware from naional semiconductor.

Phase difference
phase difference only makes sense when comparing two signals with the same frequency. When you have the phase detector working in say the PLL, it manages to find the "phase difference" between two signals of unequal frequency. I think this article needs a section explaining how this works. — Preceding unsigned comment added by Aditya8795 (talk • contribs) 15:16, 29 November 2018 (UTC)


 * This is explained in the Phase-locked_loop. ~Kvng (talk) 20:24, 27 June 2022 (UTC)

4046
''The following was contributed by. Interesting but uncited and definitely doesn't belong in the lead. ~Kvng (talk) 14:16, 1 July 2020 (UTC)

The 4046 popular IC is well known to have a centralised dead band on one phase comparator when both inputs are in phase at zero degrees difference. In fact it has been observed that the detector malfunctions. In this condition the output should not change state at all, although a small "glitch" would be acceptable. However all possible output changes have been observed between the three states! The reason for this is probably inadequate delay between outputs and resets, with erratic clears resulting. The elegant equivalent is to use two D type flip flops, one for each input. An input edge clocks its flipflop high. When both are high, an AND gate with both flipflops as inputs goes High and with a small delay incorporated clears both flip-flops. The outputs go to a differential amplifier, which acts like an exclusive OR, with no output shift when both phase comparator outputs are the same. There is no dead band and no error, the only limit being the original clock rate. This comparator is expandable. Another similar stage can sense if there has been a "mixed clock" is an extra clock edge that has been missed, store said information and use it. More simply, such a phase frequency comparator acts like an up down counter, where the loop attempts to keep it at any chosen count. If one assumes a decimal 0 to 9 counter, normally set to 5 with up down clocks as the phase inputs, the noise immunity expands up to 5 sequential pulses on one input.

Clarification on statement made in derivation
Instead of using two multipliers, a more common phase detector uses a single multiplier and a different trigonometric identity:
 * $$\sin \alpha \cos \beta = {\sin(\alpha - \beta) \over 2} + {\sin(\alpha + \beta) \over 2} \approx {\alpha - \beta \over 2} + {\sin(\alpha + \beta) \over 2} $$

The first term provides the desired phase difference. The second term is a sinusoid at twice the reference frequency, so it can be filtered out. In the case of general waveforms the phase detector output is described with the phase detector characteristic.

'In the above section, where I have put bold and underlined of the statement "The second term is a sinusoid at twice the reference frequency", I believe this is not the case unless alpha = beta which is not stated. It is indeed generally larger and able to be filtered, however I am not sure that we can say it is at twice the frequency? ' Midoriimo (talk) 00:23, 4 February 2024 (UTC)