Talk:PowerPC/Archives/2013

Instruction set vs. Microarchitecture
The current version Special/Permalink:567967225 of the article does not distinguish clearly between Instruction set and Microarchitecture. I know that e.g. x86-64 is an instruction set and Intel's Nehalem (microarchitecture) is a microarchitecture implementing it. I am not sure about the PowerISA. It seems to me, like there is the either one instruction set called Power Architecture (with different versions) or even an instruction set family. Then, so it seems, there are three main microarchitecture families implementing it: PowerPC for PCs, PowerQUICC for embedded systems and POWERx for servers.

1. Is this correct? If it was, all the articles should IMO begin with PowerPC/POWERx/PowerQUICC is a family of microarchitectures implementing the Power instruction set.
 * No, this is not correct. There are a lot of micro architectures implementing the Power ISA. Pretty all POWERn processor (POWER7 and POWER7+ use the same, POWER8 does not) use different, all generations of PowerQUICC use different (the e200, e300, e500, e500mc, e5500, e6500 cores all use different microarchs). PowerPC G3 and G4 use different (three (iirc) different microarchs for the G4s). Most new iteration use a new microarch. There are some designs that doesn't obviously use the same, such as he G5 and POWER4, the PowerEN and Blue Gene/Q, and PowerPC 440 and Blue Gene/L. The word doesn't bear the same importance for PPC or Power Arch, more what cores goes into where. -- Henriok (talk) 13:38, 4 September 2013 (UTC)
 * In the current Power ISA, a microarch doesn't have to implement the complete set, there are "Books" and they range from common to more specialized features. Book I and II are required, but Book III is split into several topics where you can't implement them all. There are subjects dealing with server oriented issues, virtualization, auxiliary accelerators, SIMD-units, embedded applications, memory management, floating point variations, 32 vs 64-bit, variable length instructions, big/small/bi endianess, and so on.
 * A low end processor implementing the Power ISA is a single 32-bit single issue, in-order core with variable length encoding, 4 stage pipeline with 3 functional units, no cache nor MMU and no FPU, running at <50 MHz (ie the Freescale e200z0).
 * A high end processor is 64-bit 12x multi-core, 8 way hyperthreaded, multi issue, out-of-order core with hardware hypervisor, ~15-25 stages long pipeline, microops-cracker, 16 functional units, large, deep and segmented cache structure (4 levels, >100 MB large), integrated SIMD-accelerators and decimal floating point, running at 4 GHz (ie the POWER8).
 * The e200z0 is implementing Power ISA v.2.03 Book III-VLE, and the POWER8 implements Power ISA v.2.07 Book III-S. Both are Power ISA compliant but quite different. -- Henriok (talk) 15:55, 4 September 2013 (UTC)

2. The x86 Instruction set is __owned__ by Intel, ARM instruction set is owned by ARM Holdings, MIPS instruction set by Imagination Technologies, Ubicom by Qualcomm, etc. Who is/are the owners of the Power Instruction set and who are the licensees? ScotXW (talk) 08:35, 4 September 2013 (UTC)
 * The ISA is owned by Power.org, while Freescale and IBM hold permanent licenses. Power.org, IBM and Freescale can issue licenses to new parties, and there are specialized brokers of licenses too. New aspects are incorporated into the ISA on a regular basis (the latest is PowerISA v.2.07 with support for POWER8 and Freescale's e6500 core), and such improvements come mostly from Freescale and IBM but can come from other members of Power.org. There are -- Henriok (talk) 13:38, 4 September 2013 (UTC)
 * The Power ISA is owned by Power.org. The former PowerPC ISA was jointly developed and co-owned by Motorola/Freescale, IBM and Apple (IBM owned the trademark). Apple dropped out, Motorola's and IBM's implementations diverged, but came back together in 2006, joined their separate PowerPC ISAs into one and called it Power ISA. -- Henriok (talk) 15:55, 4 September 2013 (UTC)

PowerQUICC
I think someone should make a separate article about PowerQUICC. It's an important part of PowerPC and Power Architecture, but it's a part that hasn't gotten a lot of main stream coverage since it's an embedded technology that pretty much just for industry insiders. The recent bloating of the "Motorola (now Freescale)" on this page is not appropriate, considering all the other similar entries on the page. A separate PowerQUICC-page, that'll both outline and bring some depth to what Motorola and Freescale have beed doing the pastyears in repsct to PowerPC development, would be very nice. There's certainly a lot to be said in such an article.
 * PowerQUICC ScotXW (talk) 08:20, 4 September 2013 (UTC)
 * Thanks! I posted that request in 2006, and just initiated the article by myself shortly thereafter :) -- Henriok (talk) 11:49, 4 September 2013 (UTC)