Talk:Program status word

Program status word register
program status word register 69.113.57.33 22:26, 11 September 2007 (UTC)

Length of PSW
The statement The program status word (PSW) is, typically, 32 bits in length. may be true for 16-bit processors but it is incorrect for 32-bit and 64-bit processors. For those 64 bits and 128 bits are more common. Shmuel (Seymour J.) Metz Username:Chatul (talk) 15:46, 16 November 2010 (UTC)
 * The page was changed from a page to talk about PSWs in ISAs including non-S/3x0 ISA to a redirect to status register in this edit, which I guess was a merge into status register, and then turned into a page talking only about S/3x0 PSWs in this edit, so the offending text is no longer present. Guy Harris (talk) 03:04, 28 December 2020 (UTC)

PSW layouts
I've copied the PSW tables from IBM System/370 and added the standard S/360 and 360/67 formats. The way those are laid out looks OK for 64-bit registers but would be too crowded for 128. I've used a different format for z/Architecture, and have a prototype at User:Chatul/sandbox/PSW; it needs some tweaking to separate words more clearly. Once that's ready to include in the PSW article, should I change the existing tables to the same style? Shmuel (Seymour J.) Metz Username:Chatul (talk) 00:52, 28 December 2020 (UTC)
 * "...should I change the existing tables to the same style?" I'd vote yes; it makes it a bit easier to determine the bit numbers of the bit fields in the PSW.  (And change them in IBM System/370 as well.  z/Architecture should perhaps be expanded as well, with its own table, similar to the one in IBM System/370.) Guy Harris (talk) 06:51, 28 December 2020 (UTC)
 * In IBM System/370 there is the issue of consistency with the other register layouts. Or do you think that those should be changed as well? Shmuel (Seymour J.) Metz Username:Chatul (talk) 07:57, 28 December 2020 (UTC)
 * Yes, change them all. Guy Harris (talk) 18:40, 28 December 2020 (UTC)
 * Yes, too. And thanks for all the hard work.  Tom94022 (talk) 07:33, 28 December 2020 (UTC)
 * I've tweaked it a bit to put in more white space; please edit it or post a comment if you don't think I have the spacing or font sizes quite right. Also, I need to link the z PoOp. Shmuel (Seymour J.) Metz Username:Chatul (talk) 17:38, 28 December 2020 (UTC)

PSW in other architectures
The concept of a PSW is not limited to IBM System/360 and successors; it exists both in other IBM products, e.g., 8100, and in products from other vendors, e.g., SDS Sigma series, although the nomenclature varies. I'd like to include an appropriate notice that the article is limited in scope, but there's no DAB or generic article to point to with a hatnote. I don't want to put in detailed information about the other vendors because it might make the article unwieldy. Suggestions? Shmuel (Seymour J.) Metz Username:Chatul (talk) 19:35, 31 December 2020 (UTC)
 * I suppose it would be too much to include others here, though that suggests giving it a more specific name. VAX has PSL, Program Status Longword, (since word is defined as 16 bits, even though it is a 32 bit architecture). The instruction address is in R15, separate from the PSL. That could be somewhere in WP, as VAX was pretty popular. I am not sure of the actual names for the other ones you mention. Gah4 (talk) 00:57, 9 February 2024 (UTC)
 * A similar issue existed in Control register, which was originally Intel only. Ideally at least a half dozen architectures should be shown for each. I don't have a strong opinion as to whether to split the articles. -- Shmuel (Seymour J.) Metz Username:Chatul (talk) 14:38, 12 February 2024 (UTC)
 * The PDP-11 architecture also has a register, called the "Central Processor Status Register" in the 1972 PDP-11 Handbook (the cover just mentions the 11/20, 11/15, and 11R20, but the manual itself mentions the 11/45 and the 11/05) and the "Processor Status Register" in one image and "Processor Status Word" in the text of the 19679 PDP-11 Processor Handbook. That register, like the VAX PSL, contains condition code bits, a "trap when the next instruction completes" bit (for single-stepping in a debugger), and the current interrupt priority level and, in the models that have privilege modes, the current and previous privilege mode (Kernel, Supervisor on machines that support it, and User mode). That's separate from the PC, which is register R7; the VAX picked that split, and the PC being the highest-numbers register, from the VAX. Guy Harris (talk) 20:16, 12 February 2024 (UTC)
 * The VAX Architecture Reference Manual mentions the PDP-11 PSW, in addition to the VAX PSL, presumably because of compatibility mode. We could have one, slightly general, article, and then links to the specific articles. Gah4 (talk) 02:28, 13 February 2024 (UTC)
 * The Intel 8080 likewise has a PSW. The accumulator and the flags together are called the program status word. There are PUSH PSW and POP PSW instructions. I think including every possible PSW into this article will muddle it. The solution might be a list under a new heading "PSW in other architectures" with a link to its corresponding article. RastaKins (talk) 15:53, 30 March 2024 (UTC)
 * The VAX Architecture Reference Manual mentions the PDP-11 PSW, in addition to the VAX PSL, presumably because of compatibility mode. We could have one, slightly general, article, and then links to the specific articles. Gah4 (talk) 02:28, 13 February 2024 (UTC)
 * The Intel 8080 likewise has a PSW. The accumulator and the flags together are called the program status word. There are PUSH PSW and POP PSW instructions. I think including every possible PSW into this article will muddle it. The solution might be a list under a new heading "PSW in other architectures" with a link to its corresponding article. RastaKins (talk) 15:53, 30 March 2024 (UTC)