Talk:SPARC/Archives/2018

Infrant IT3103 and IT3107
As concrete (and heavily productized!) examples of embedded SPARC, it would be useful if we could dig up more information on the Infrant Technologies' IT3103 and IT3107 LEON2-based SPARC processors used in the Infrant (later NetGear) ReadyNAS NV1 boxes starting from 2005; eg configured on-chip cache sizes, process-node/die-size, power (W), no. I/O pins. We can surmise some details from the non-configurable parts of LEON2 (ie: threads/cores, arch. version) and some from the press releases and historical product brochures (ie: year 2005). Shelldozer (talk) 14:03, 19 September 2017 (UTC)
 * http://www.businesswire.com/news/home/20050404005773/en/Infrant-Technologies-Introduces-IT3100-Network-Storage-Processor
 * http://www.eetimes.com/document.asp?doc_id=1195625
 * http://debugmo.de/2007/07/running-own-code-on-the-infrant-readynas/

Open and Royalty free
The Template:Infobox CPU architecture currently says the instruction set is "open" and "royalty free".
 * royalty free means, that – in contrast to the x86 or the ARM instruction set – anybody is free to implement an own microarchitecture base on it. Am I correct?
 * what does "open" mean? User:ScotXW t@lk 10:14, 3 March 2018 (UTC)