Talk:Sandy Bridge/Archive 1

OpenCL compatibility
Does it support OpenCL 1.1, as it was promised by Intel ? —Preceding unsigned comment added by 213.108.2.36 (talk) 10:14, 15 January 2011 (UTC)

Teraflop processor
http://news.com.com/Intel+pledges+80+cores+in+five+years/2100-1006_3-6119618.html?tag=nefd.top

there might be a correlation.

Intel pledges 80 cores in 5 years. that's right aroudn the proper time period. Based on that ti would not be unreasonable to speculate that Intel would be using 20 through 40+ core on Gesher.

pure speculation though


 * No, the teraflop 80-core processor is a completely different beast that has very little to do with Gesher. See http://www.dailytech.com/Intel+Takes+the+Hood+Off+TeraScale+Computing/article6057.htm. Gesher will the evolutionary based on an evolved formed of the Core 2 Duo, while the teraflop chip is revolutionary, just as Conroe was revolutionary after NetBurst. --Conquerist 23:25, 3 March 2007 (UTC)

Found a contradiction in the node size
The main Intel Core 2 article, currently under the Successors heading, claims that the size is speculative and may be at 22 nm (with Nehalem possibly at 32 nm), while this article is toned in a way to not only make it sound more definite, but also that it's to be a 32 nm size. I'm not sure if it's speculation in this article as well, and in that case it needs to be marked so, and preferrably also agree with the other Wikipedia article. :-) -- Northgrove 15:48, 31 January 2007 (UTC)


 * The Core 2 article now states that Gesher will be based on the 32 nm process. Additionally, I have cited that Gesher is 32 nm both in this article and in the Core 2 Article. --Conquerist 23:25, 3 March 2007 (UTC)

Rename article?
Shouldn't the article be renamaed to "Sandy Bridge (microarchitecture)" (together with the Nehalem (CPU architecture) and Intel Core (CPU architecture) articles) to avoid using the word "architecture" for microarchitecture (hardware) and instruction set (software) possibly confusing a bit?
 * I suggested on Talk:Nehalem (CPU architecture) that we rename Intel Core (CPU architecture), Nehalem (CPU architecture), and Sandy Bridge (CPU architecture) to "Intel Core (CPU microarchitecture)", "Nehalem (CPU microarchitecture)", and "Sandy Bridge (CPU microarchitecture)". My reason is that the terms "architecture" and "microarchitecture" refer to different things.  "Architecture" is for the overall design of the processor (as in the ISA), such as x86, POWER, Alpha, SPARC, etc.  Microarchitecture, on the other hand, refers to the specific implementation of the design.  CPUs with different architectures are not compatible, but those with different microarchitectures are compatible.  That's my idea, what do you think?  (And yes, I just copied this post from Talk:Intel Core (CPU architecture)) Imperator3733 23:50, 24 September 2007 (UTC)


 * I mentioned at Talk:Intel Core (CPU architecture) a new, revised idea for renaming these articles. The idea is to rename the articles to Intel Core (microarchitecture), Nehalem (microarchitecture), and Sandy Bridge (microarchitecture).  Another possibility would be to have "Intel" in all the names (making the naming more consistent -- i.e. Intel Nehalem (microarchitecture) and Intel Sandy Bridge (microarchitecture).  If we do that I would suggest making the change to other uArch pages (i.e. NetBurst to Intel NetBurst (microarchitecture), Intel P6 to Intel P6 (microarchitecture), etc).  What do you think?  I'll give this a week for comments.  If the response is favorable, I (or someone else) will/can rename them.  If there is no response, I'll probably wait a bit longer.  If anyone sees this, please respond.  Thank you. -- Imperator3733 00:22, 16 October 2007 (UTC)


 * The pages have now been renamed. See Intel Core (microarchitecture), Nehalem (microarchitecture), and Sandy Bridge (microarchitecture) -- Imperator3733 18:06, 24 October 2007 (UTC)

Tick-tock?
Can someone change this term to something un-jargony? —Preceding unsigned comment added by Alwayswiththequestions (talk • contribs) 22:36, 5 January 2008 (UTC)


 * Tick means a shrink to a smaller process technology, with minor changes to the design. Tock means a major design change on the same process as the previous Tick.  For more information, see Intel Tick Tock.  -- Imperator3733 (talk) 16:52, 21 February 2008 (UTC)


 * What platform will Sandy Bridge be released on? And where does the Montevina platform (2008) fit in the tick-tock model? Or can a new platform be released any time? But then, isn't there also supposed to be such model for platforms?
 * Tock - Intel Core microarchitecture
 * Tick - Shrink/derivative (Penryn)
 * Tock - New Intel microarchitecture (Nehalem)
 * -- 83.101.9.165 (talk) 17:50, 27 February 2008 (UTC)


 * Montevina uses Penryn processors, so it would be a Tick. I'm guessing that Sandy Bridge would use a similar platform to that used by Nehalem (QPI/PCIe), but I don't know for sure. -- Imperator3733 (talk) 21:48, 27 February 2008 (UTC)

AMD's instruction sets and Intel?
Will Sandy Bridge contain SSE5, MMX+, 3DNow! and 3DNow!+ instruction sets? Please, add that info also to the main article. Urvabara (talk) 11:37, 21 February 2008 (UTC)


 * I'm not sure, but I think 3DNow! and 3DNow!+ are pretty much obsolete. Intel has never supported those instruction sets, so I don't think they would do so with Sandy Bridge.  I have never heard of MMX+ -- could you please link to some information on it?  I don't know if SSE5 will be included -- the time frames work out, but there haven't been any announcements one way or the other (I think).  -- Imperator3733 (talk) 16:49, 21 February 2008 (UTC)
 * See this picture . See also and . Is there any way to contact Intel engineers? I would like to know why not to support AMD instruction sets. Urvabara (talk) 16:03, 22 February 2008 (UTC)


 * That's the first time I've ever seen anything on MMX+. I guess its just integer SSE, so it seems to me that Intel probably supports those instructions (I think SSE2 added integer instructions).


 * As far as contacting Intel engineers, Intel doesn't publish contact information for its employees, but it does say that the email format is generally first.last@intel.com or first.middle_inital.last@intel.com (I think I'm remembering that correctly). Of course you have to know an employees name before you can use that.  You could always try using Intel's "Contact Us" page, but my experience with that has been pretty bad.  First they try an automated response that tries to analyze your message to provide possible links to your question (which has never worked for me), and then you need to escalate your question to a human.  I have never gotten a satisfactory answer from them, but maybe you will.  Good luck.  -- Imperator3733 (talk) 22:17, 27 February 2008 (UTC)
 * Thanks! Urvabara (talk) 08:06, 28 February 2008 (UTC)

MMX+ probably yes. SSE5 maybe. But 3DNow! and 3DNow!+ deffinietly not. Intel never implemented them (and had 10 years to do this), and even AMD is removing them from CPU. But it is just my opinion. --91.213.255.7 (talk) 00:03, 8 January 2011 (UTC)

Processor roadmaps
I've started a discussion on the processor roadmap graphics over at Talk:Nehalem (microarchitecture). Please take a look and make a comment if you have any thoughts. Thank you. -- Imperator3733 (talk) 15:06, 11 June 2008 (UTC)

Keifer
Should the section on Keifer even be in this article? It doesn't seem like it fits. -- Imperator3733 (talk) 18:41, 2 July 2008 (UTC)

i agree, it seems irrelevant and should be removedNicoli nicolivich (talk) 00:21, 16 November 2008 (UTC)

Socket for Sandy Bridge
It is probably much too early to speculate, but I wonder if Intel will be using LGA1366 for Sandy Bridge? I know Westmere should be using it, but I am quite curious as to Sandy Bridge. LGA775 supported P4 up to Core 2, and LGA1366 would seem to be able to support a processor such as Sandy Bridge--though I am not so sure about the apparent bus improvements. --Marsbound2024 (talk) 01:08, 23 November 2008 (UTC)


 * It seems, that Sandy Bridge will be using following Sockets: For desktop, LGA 1155, server LGA1365 (1-2 sockets Jaketown, 4-8 C + HT, dual channel mem), AND LGA2011 (1-4 sockets, 4-8C + HT, quadruple channel), also heading for high-end desktop.

Ivy Bridge will be using same sockets. —Preceding unsigned comment added by 192.198.151.36 (talk) 10:48, 4 February 2011 (UTC)
 * Citation?Jasper Deng (talk) 00:20, 5 February 2011 (UTC)

Translation Lookaside Buffer Cache.
Does anyone know the TLB cache size of Sandy Bridge ? For some reason this information is impossible to find - and it is very important for large applications.

Is it per die ? Per core ? Per hyper thread ? —Preceding unsigned comment added by 82.95.66.103 (talk) 18:38, 13 December 2009 (UTC)

Any Idea where this came from
"Nehalem may stay at the server platform while Sandy Bridge is released for the mobile segments, which would split the markets into two CPU lines."

This statement is highly speculative. The article mentions it might be split but does not indicate it will be split or indicate segments splitting. High-end chip (servers & gaming PC) tend to get the best margins so rarely will they not get the latest and greatest first. Mobile segments tend to be a follow on a few months later with mainstream and value chips holding up the rear. Did who ever write this in speak the language natively since machine translations can be problematic. In any case most of the items from the PC watch section should be reviewed after IDF in april. —Preceding unsigned comment added by 98.162.247.51 (talk) 07:17, 11 March 2010 (UTC)

The 4P and 1-2P isn't consistent
I really doubt the Sandy Bridge EX CPU will be just 4 sockets at most, because Nehalem EX clearly was also for more than 4 sockets, 8 or more. This should be replaced with MP (multiprocessor). The 1-2P also is not consistent because it doesn't differ UP (Uni-processor) or DP (Dual processor).Jasper Deng (talk) 03:07, 1 April 2010 (UTC)

Intel will split the EX market into two sections. Westmere-EX and then Ivy Bridge-EX-A succeed Nehalem-EX in the high-end of that market, while Sandy Bridge-EX and Ivy Bridge-EX-B succeed Nehalem-EX in the low-end of that market. 76.192.138.36 (talk) 20:28, 30 April 2010 (UTC)

Article is out of date regarding socket 1356.
Sandy Bridge will be released Q1 2011 for socket 1155 and the high-end will be released Q3 2011 on socket 2011.

Socket 1356 has been scrapped, and the table needs to be updated as such.

according to pcmag. the release date according to intel is q4 2010 -Tracer9999 (talk) 10:56, 29 April 2010 (UTC)

Link for socket 1356? And that PC Mag article says Q4 2010 for production, not release. 76.192.138.36 (talk) 20:28, 30 April 2010 (UTC)

Edit: It says production and shipping 76.192.138.36 (talk) 20:30, 30 April 2010 (UTC)

http://www.bit-tech.net/hardware/cpus/2010/04/21/intel-sandy-bridge-details-of-the-next-gen/

http://vr-zone.com/articles/a-look-into-intel-s-next-gen-enthusiast-platform--sandy-bridge-e--waimea-bay/8877-1.html|title=New

Both of these recent articles have no mention of 1356, but do mention 2011 for the highend desktop space and 1155 for the mainstream. Q4 2010 is stated as possible, but up to change.

Update variants table PLEASE!
This table has been quite out of date, and no-one's fixing it. I don't have the time to fix it. Can someone please fix it? Or shall we delete this section due to insufficient citations?Jasper Deng (talk) 02:38, 4 May 2010 (UTC)

Continued vandalism by 75.57.77.40
I'm not sure of the proper procedure, but this IP continues to edit the technical specs into unprecedented values without source, and continues to edit them despite reversion. —Preceding unsigned comment added by 98.27.85.106 (talk) 21:46, 27 May 2010 (UTC)


 * The same user evidently also vandalized other pages, and used at least two addresses, see Special:Contributions/75.57.77.40 and Special:Contributions/75.57.67.43. Arndbergmann (talk) 01:24, 28 May 2010 (UTC)

32-core and 50+-core Sandy Bridge chips
http://www.itworld.com/hardware/109481/intel-unveils-new-server-chip-32-cores

Intel unveiled 32-core chips for servers. These chips were said to be part of the Sandy Bridge microarchitecture. —Preceding unsigned comment added by Jasper Deng (talk • contribs) 16:52, 31 May 2010 (UTC)


 * According to, these chips are Larrabee, not Sandy Bridge. Indeed, putting that many general purpose cores on one chip would make the size explode even at 22 nm, so a simplified larrabee core seems much more plausible. Arndbergmann (talk) 21:11, 31 May 2010 (UTC)
 * Well, Intel Knights redirects to this article. Either we remove this redirect and make it it's own article, or we include this in this article.Jasper Deng (talk) 18:38, 27 December 2010 (UTC)

Transition
The article currently says: "If the transition to 32 nm is difficult, then Sandy Bridge may go over three generations (Sandy Bridge, Ivy Bridge, and another Bridge) as opposed to two with Core 2 and Nehalem."

Somehow, I think this doesn't make much sense. Why should a transition to 32nm influence things if the architecture starts out at 32nm ?!?

Also, the article linked as source for this seems to talk a LOT about the transition to 22nm. I think this is currently wrong in the wikipedia page and "32 nm" in the sentence should be fixed to "22 nm". —Preceding unsigned comment added by 93.203.214.239 (talk) 12:38, 7 June 2010 (UTC)

Confusing spec item about SSE
There's at main page said:

The specifications are reported to be as follows:

* ...... * Without SSE: 8 DP GFLOPS/core (2 DP FP/clock), 32 DP GFLOPS per processor. * With AVX: 32 DP GFLOPS/core (8 DP FP/clock), 128 DP GFLOPS/processor.

And from this follows that it does not support SSE, but support AVX.

Maybe it's not what was implied by that phrase, but this is the meaning it delivers.

And it's not true, since it will support all previous instructions including SSE + new AVX instructions.

GFLOPS should be removed from spec list, and those two items changed to something like: * it will support SSE (and all other previous instructions) + new AVX instructions or simply * it will support new AVX instructions —Preceding unsigned comment added by 93.73.4.74 (talk) 14:28, 12 September 2010 (UTC)

I think it is messed up, becuase AVX instructions actually shares registers in some part with SSE! Some you cannot just use AVX and SSE in the same time to compute something even faster as, at first one will mess registers of, and SSE instructions are probably implemented using subunit of AVX. Just my theory, but have probably sense, becuase if one will run old code, the AVX will be unused and waster, similary if one will use new AVX code, on the other hand SSE unit will be idle and wasted. Because it would be very hard to write code which will use AVX and SSE in the same time (really hard manually in assembly, not to mention that no compiler is prepared for such chelenge either), I can state that it is probably just one floating point unit which can be used fully AVX, or in "SSE" mode where it works only on half of the data. It is also probably that CPU actually performs internal translation from two-operand SSE into three-operand AVX + flag to operate only on half of registers (to not destroy registers on write and to not dissipate to much heat). --91.213.255.7 (talk) 00:01, 8 January 2011 (UTC)

Similary for example AES-NI also operates on the registers of the SSE. --91.213.255.7 (talk) 00:01, 8 January 2011 (UTC)

L1 and L2 cache latency correction
A new extensive article about Sandy Bridge architecture (http://www.realworldtech.com/page.cfm?ArticleID=RWT091810191937&p=7) points to different values for L1 and L2 cache load-to-use latencies, as follows:

L1 is 4 cycle (same as Nehalem), not 3.

L2 is 12 cycles, not 8.

--Fellix 15:08, 27 September 2010 (UTC) —Preceding unsigned comment added by Fellix (talk • contribs)

More News on the Sandy Bridge
Hi everyone,

I am brand new to Wikipedia, and really hope I am not messing anything up with my first discussion post here. I "joined" because I saw the last edit to this area was September 27, 2010 and there's been a great deal going on in various technical discussion boards that I participate in on a daily basis.

I'm not sure how often the group here convenes to discuss what to put in, remove, or edit from the main article. I'm also not sure how to cite sources like you have done, but I am reading up on it. I'd like to offer new material rather than correct some mistakes I see (people often hate having their errors pointed out) so I'd like the discussion to focus on what is not in the article right now that I think would benefit by being brought into the fold.

How does that sounds?

Thanks in advance.

Bit XOR or NAND (talk) 02:22, 8 November 2010 (UTC)


 * Moved information from "Architecture" into a separate "Overclocking" area. Added more info from press releases in September 2010 from ZD Net (reliable media source).

Bit XOR or NAND (talk) 22:55, 10 November 2010 (UTC)


 * In general there is no meaningful coordination before editing except on articles with severe problems or where major changes are being made. If you think something should be changed, be bold (but be prepared to discuss if someone else disagrees).  And please correct anything that is factually inaccurate.  It's unlikely you'll bruise anyone's ego (they are unlikely even to notice the edit), and if their ego does get bruised then they deserved it. —  Aluvus  t/c 07:52, 11 November 2010 (UTC)

Factual Inaccuracy on socket 1356?
It seems like there's only been one IP (175.156.218.35) continuing to mention (and aggressively edit for) a socket 1356, but from every news source from the last ~5 months I've read there's no mention of 1356 at all, only 1155 and 2011. Additionally, the one IP uses one source -- an outdated Japanese article. Looking at the history, it seems that prior to ~November 4th there were ~12+ sources confirming sockets 2011 and 1155, but they're been removed for that Japanese article.

What is the general consensus on socket 1356? The only sources I've been able to find supporting it are at least 4 months old, everything newer contradicts that.

Sp12.07 (talk) 01:10, 12 November 2010 (UTC)

I have a friend who's an Intel engineer and there is no such thing as socket 1356, it was scrapped in like May. —Preceding unsigned comment added by 98.27.85.106 (talk) 21:46, 26 December 2010 (UTC)

Broken Reference
Reference 24 is a broken link. I was trying to verify the release date of the processors, but the citation is broken. If anyone can fix this that would be great. — Preceding unsigned comment added by TrieBr (talk • contribs) 19:49, 9 December 2010 (UTC)

16-core Ivy Bridge
Please do not say Ivy Bridge will have 16 cores (not even saying possibly or probably). It's pure speculation unless someone can find a reliable reference. Even though I'd like it that way, it can't stay unfortunately until someone fins a reliable no-speculating reference for that. Reference 32 did NOT talk about 16-core Ivy Bridge-only speculating about 16-core Sandy Bridge, and it being speculation, it doesn't cut it.Jasper Deng (talk) 06:01, 22 December 2010 (UTC)


 * agreed. Does this suffice? http://translate.google.com/translate?js=n&prev=_t&hl=en&ie=UTF-8&layout=2&eotf=1&sl=auto&tl=en&u=http%3A%2F%2Fwww.hardware-infos.com%2Fnews.php%3Fnews%3D3214 -- it does not expressly say it, but it does say that is the first on 22nm after the 32nm build. and the photograph appears to show 16 cores (and the transistor count is up from a quad at 0.7 to 2.9 billion .. about 4 times the quad core count). --108.28.13.59 (talk) 19:59, 4 January 2011 (UTC)
 * No, it's clearly an 8-core. Do not use transistor count to do that. The amount of transistors per core is NOT fixed. It doesn't suffice.Jasper Deng (talk) 05:40, 5 January 2011 (UTC)

Is it normal some have it on pre-order?
Article says it's introduced in 5 Jan, but it's on preorder online for days. --AaThinker (talk) 23:12, 4 January 2011 (UTC)

AES encryption
Quote from article: "AES encryption will be available for both video conferencing and VoIP applications.[19]" AFAIK AES-NI can be used for anything you want, file encryption, archive encryption (i.e. winrar), ipsec, full hard-drive encryption using multiple operating systems (windows, linux, etc) and multiple solutions, https servers and clients, tls, voip, video, etc. So I do not understand this quotes, especially that AES-NI is already available in some CPUs since 2009. —Preceding unsigned comment added by 91.213.255.7 (talk) 23:52, 7 January 2011 (UTC)

What's the socket name of the laptop?
It's not listed. --62.1.89.9 (talk) 18:25, 11 January 2011 (UTC)
 * There isn't an article on it. People on the internet don't provide us sources.Jasper Deng (talk) 22:10, 18 January 2011 (UTC)

Assertion of a new naming convention
I think that it would be proper for wikipedia to disambiguate the different core i series processors by using core i for the originals and core 2i for the new ones. e.g. core i5 vs core 2i5. This will remain a source of confusion for average buyers whether they are on wikipedia or tigerdirect. If a new standard were started, it could benefit the world community. Coder543 (talk) 21:55, 16 January 2011 (UTC)coder543
 * I think this suggestion is no more than complication for complication's sake. Considering that a 2 has already been added to the part numbers(i5 2500 vs. i5 750), and that Core 2 already exists as a separate product, this proposed convention will do more harm than good.
 * 67.190.4.58 (talk) 23:29, 17 January 2011 (UTC)
 * Wikipedia follows how everything is actually branded. Wikipedia isn't a shopping site, remember. As such I oppose this.Jasper Deng (talk) 22:09, 18 January 2011 (UTC)

8-core Core i5 and 12-core Core i7?
http://www.winsupersite.com/article/hardware/2011-Hardware-Trends.aspx The only other possibility is that Paul here is confused about cores vs. threads. Should it be added? — Preceding unsigned comment added by Jasper Deng (talk • contribs) 00:21, 19 January 2011 (UTC)

WP:Crystal Ball
The "Speculation" (in the Architecture section) seems to me a violation of WP:CRYSTAL BALL.Jasper Deng (talk) 18:02, 25 January 2011 (UTC)
 * If no-one objects, I'm going to delete anything I deem a violation of WP:CRYSTAL BALL, especially those sentences that actually include "speculated". — Preceding unsigned comment added by Jasper Deng (talk • contribs) 21:02, 26 January 2011 (UTC)

Flaw found
Intel finds flaw in Sandy Bridge chipsets, halts shipments. Very relevant, gotta keep an eye on these news. -- Stormwatch (talk) 21:32, 31 January 2011 (UTC)
 * Let's add it, but be wary of WP:CRYSTAL BALL.Jasper Deng (talk) 05:06, 3 February 2011 (UTC)

availability
talking about availability, Core i3-2100T seems to be the only low power processor available boxed, but i wonder if end-users can get to purchase it. And i do hope to get the pentium G620T. Just sharing my thoughts. user:xxxxxl —Preceding unsigned comment added by 175.156.223.51 (talk) 11:58, 25 February 2011 (UTC)

LGA 1356
Seems that LGA1356 is showing up on the server side, desktop side no idea. Maybe they tired of people complaining too many sockets? what do we do about the LGA1356? Core i5-2310 http://www.cpu-world.com/news_2011/2011022402_Bits_and_Pieces_new_Pentiums_Core_i3-2310_and_more.html should we put it in? —Preceding unsigned comment added by 175.156.214.130 (talk) 10:58, 6 March 2011 (UTC)

Vpro and Xeon
Announced on 7th march(8 march at my side if you remember my change), but will probably release next month according to websites. —Preceding unsigned comment added by 175.156.192.212 (talk) 09:21, 9 March 2011 (UTC)

Mobile CPU sockets
It came to my attention that the mobile CPU section is missing a socket column. This had me on a wild goose chase for a few hours as I looked for some of these CPU mistakenly (stupidly) believing they were LGA1155, until I found one myself, being of BGA1023 socket. 87.194.40.167 (talk) 20:01, 31 August 2011 (UTC)

New processors need to be added
http://www.anandtech.com/show/4734/intel-releases-new-sandy-bridge-processors-price-points — Preceding unsigned comment added by Greg440 (talk • contribs) 04:06, 9 September 2011 (UTC)
 * They were already in the article? Thue | talk 06:31, 9 September 2011 (UTC)
 * The desktop processors are in the article but the new mobile processors are not. Greg440 —Preceding undated comment added 23:54, 9 September 2011 (UTC).

bull mountain
If the source didn't come directly from intel, I would be calling it a pile of bull.. Is there any reason we need to reference the code name for the RDRand instruction, given there's already a full page on that instruction elsewhere and we already have the proper name for it? --71.191.154.10 (talk) 17:44, 23 September 2011 (UTC)
 * My guess is that the code name refers to the (nontrivial) hardware that supports the instruction. It's not like AES or some other instruction that implements a pure computational algorithm.  It's something like an analog or mixed-signal circuit on the chip.  The code name is useful for further research (web searches) so should stay in the article.  E.g. I just found this by searching on it. 71.141.89.0 (talk) 18:04, 24 September 2011 (UTC)

Logos
Are the logos really required? How does it help someone when the logos are there? 202.21.158.11 (talk) 04:44, 7 October 2011 (UTC)

No LGA 1356 socket
According a Intel roadmap leaked by Xfastest it will not come any LGA1356 socket. http://www.xfastest.com/cms/tid-57986/ —Preceding unsigned comment added by 81.227.2.148 (talk) 18:20, 27 March 2011 (UTC)
 * I surmise that if it appears, it will be server segment only. Azul120 (talk) 05:05, 14 April 2011 (UTC)
 * Is there any real evidence it will be coming at all other than a few very old news articles? 86.22.248.209 (talk) 12:13, 10 October 2011 (UTC)

Removing of Price?
Hi! I was thinking of removing the price from the cpu list, and as an alternative, we could put a link to the intel website where people can see intel's price. What do you all think? 175.156.196.163 (talk) 23:22, 24 October 2011 (UTC)
 * The volume price per unit is a rather important piece of CPU info.Jasper Deng (talk) 23:26, 24 October 2011 (UTC)
 * How is it important? We are not so free to change it all the time, and wiki rules also states something about price. A not updated price could also lead to some problems down the road? 202.21.158.11 (talk) 01:04, 25 October 2011 (UTC)
 * I agree. The idea by the OP for putting in a link seems to be prudent. AdventurousSquirrel (talk) 01:07, 25 October 2011 (UTC)

Yes, you might recall that i have added this link(http://ark.intel.com/products/codename/29900) to intel page showing all sb processors, the price and spec. So i think that is good enough. I don't think we would want to cause trouble just because maybe some price is not updated properly? 175.156.196.163 (talk) 09:14, 25 October 2011 (UTC)
 * I think the price list is violating WP:NOPRICES rule. Those should be removed from this article. Shigeru23 (talk) 11:59, 22 November 2011 (UTC)


 * If the prices are to be retained, as per WP:NOPRICES references need to be improved to demonstrate where the prices came from and why including them is important. This information does not exist. Better to omit. --Kvng (talk) 15:29, 22 November 2011 (UTC)
 * Perhaps better explanation could be added, but the use of prices here is not meant as a catalog as few people buy raw chips by the thousand, and those people already know the prices. These prices have historic value and are therefore encyclopedic.Objective3000 (talk) 17:53, 22 November 2011 (UTC)
 * Why would the prices have a historic value? Even they do have value, the prices are still available on intel's website itself.203.116.251.231 (talk) 08:58, 25 November 2011 (UTC)

Removing of logos
The logos have no purpose whatsoever. I'm planning to remove them, but i would like to gather some feedback first. Decision will be based on 75% of votes from replies. 203.116.251.231 (talk) 09:01, 25 November 2011 (UTC)

QPI
Did intel eliminate the QPI? 175.156.209.83 (talk) 05:56, 26 November 2011 (UTC)
 * No.Jasper Deng (talk) 05:56, 26 November 2011 (UTC)
 * So the server segment still has QPI? Intel is moving to PCH.175.156.209.83 (talk) 06:56, 26 November 2011 (UTC)
 * PCH?? There's no source for that.Jasper Deng (talk) 18:18, 26 November 2011 (UTC)
 * I meant intel is moving to the PCH generation. so i wonder if there is no more QPI. But i guess they still use QPI for connection between multiple CPUs. 175.156.214.110 (talk) 15:19, 27 November 2011 (UTC)

Voltages?
Should we add them to the tables? — Preceding unsigned comment added by 46.170.68.186 (talk) 13:00, 4 January 2012 (UTC)

Ivy Bridge differences
This is not formatted correctly. Ivy Bridge is very different, especially with the 3D transistor gates. This is like saying Sandy Bridge is like Nehalem or Westmere is like Nehalem.Jasper Deng (talk) 04:56, 5 January 2012 (UTC)
 * I've formatted it correctly. I hope this prevents the edit war. Sincerely, Akjar13 (He's Gone Mental) 08:51, 5 January 2012 (UTC)

Random Xeon question
If SB-E has a maximum of 8 cores, then how was Westmere able to max out at 10 for Xeon? Or is it sort of apples and oranges between the desktop and Xeon CPUs? --Azul120 (talk) 06:27, 5 January 2012 (UTC)
 * 10 will also be the maximum for SB-E.Jasper Deng (talk) 06:28, 5 January 2012 (UTC)
 * According to http://realworldtech.com/page.cfm?ArticleID=RWT072811020122 and others, there will likely be no Xeon E7 version of Sandy bridge, but only a Xeon E3 and E5. Westmere-EX is for the high-end market with up to 8 sockets that is now branded Xeon E7 and it would be reasonable to expect this to skip Sandy Bridge but continue with an Ivy Bridge-EX based Xeon E7. I think none of these have been confirmed though, so it doesn't belong into the article (yet). Die photos of SB-E suggest that they will all come with 8 cores but may have some of those disabled, as in the Core i7 products. Arndbergmann (talk) 09:55, 5 January 2012 (UTC)

Contradiction in L2 size
The article says (in the bullet points) that Sandy Bridge will have 2048KB of L2 per core, while the table at the end of the article says it will have 256KB of L2 per core. 2048KB L2 seems a bit unrealistic. Nehalem only has 256KB.

-- ssj4Gogeta

Printable html format of processor overview
Please change the html format of the overview of the different processors so that it becomes printable or at least can be copy/pasted into a e.g. a Word document.

Sandy Bridge Celerons
The upcoming Celeron processors, which are based on Sandy Bridge, should probably be put in the market sector chart.

Dell's 2450m
Someone edit this CPU into the list i dont know how. 91.140.67.78 (talk) 08:56, 15 February 2012 (UTC)

1P, 2P, 3P...
Hey guys, I'm not much of a hardware guy... what does 1P, 2P, or 3P mean. 96.245.78.16 (talk) 23:15, 9 February 2012 (UTC) --> it means plattforms with 1 processor, 2 proccessor, etc. — Preceding unsigned comment added by 92.75.1.148 (talk) 04:30, 18 February 2012 (UTC)

New Xeon E7 CPUs
Where are the new Xeon E7 CPUs? — Preceding unsigned comment added by 137.193.120.89 (talk) 13:03, 17 January 2012 (UTC)

Three new processors
Could someone add these into the list?

http://www.cpu-world.com/news_2012/2012012901_Three_new_Core_i5_CPUs_added_to_Intel_pricelist.html

Ppw0 (talk) 05:35, 19 March 2012 (UTC)

Silent removal of information that doesn't suit Intel
It's frustrating to see edits from unregistered users that change more-or-less subtly things so they sound better for Intel. Usually with no written comment, or a comment talking about something else. I just partially reverted one such change that removed all references to Sandy Bridge's DRM. That is so wrong. Is there a way to publicly expose such behavior? --jbc (talk) 12:46, 12 March 2012 (UTC)
 * No, wiki editors like me change things base on source, and not to "make things sound better for intel". "I just partially reverted one such change that removed all references to Sandy Bridge's DRM.": your change did not add any source btw. and again, you called it drm without showing any proof that it is indeed drm.175.156.218.73 (talk) 03:58, 15 March 2012 (UTC)
 * There was a reference to an article where it is explained clearly why it is DRM. What do you mean by "editors like you"? The change was made from an IP and not from a registered account, and furthermore it added no explanation, simply a silent removal of the information. Please stop doing it. --jbc (talk) 23:11, 21 March 2012 (UTC)
 * You are simply being unreasonable, there is still no prove to show that it is DRM. (I do have a wiki id btw)175.156.206.232 (talk) 09:22, 23 March 2012 (UTC)

Sandy Bridge Pentium doesn't support AVX
I was confused by this article, ended up with spending all morning for nothing.. http://en.wikipedia.org/wiki/List_of_Intel_Pentium_microprocessors#Sandy_Bridge_based_Pentiums this article says more clearly — Preceding unsigned comment added by 222.99.91.229 (talk) 05:15, 30 March 2012 (UTC)

New Xeon E3-1200 V2 CPUs
Not sure how these should be added. New "V2" table, or should the go in with the V1 models? -- Big Brother 1984 (talk) 21:39, 27 June 2012 (UTC)

Intel Pentium G640
I just came to see values for the Intel Pentium G640. Is there a reason why it is not in the list? http://ark.intel.com/products/53486/Intel-Pentium-Processor-G640-3M-Cache-2_80-GHz djk --93.220.60.156 (talk) 08:36, 9 September 2012 (UTC)

Sandy Bridge
Why does Sandy Bridge redirect here? If this is the primary use, shouldn't it be on the Sandy Bridge page? — Preceding unsigned comment added by 216.249.56.82 (talk) 09:25, 9 September 2012 (UTC)

QPI Speeds for E/EN/EP Xeons
What do you feel about entering the QPI speeds for the Xeons here?--Azul120 (talk) 04:00, 30 September 2012 (UTC)

Photo missing?
The caption of the photo reads "the back side of the same CPU" but there is no "top side"/"front side" photo, or a reference to what CPU is that. I can guess from the photo, but other people can at most imagine that is "some" SB CPU. The top-side photo should be added (it is linked in another intel-related articles) — Preceding unsigned comment added by LaurV (talk • contribs) 03:05, 30 October 2012 (UTC)

re. cores (threads) in "List of Sandy Bridge processors"
It's not clear whether "threads" means number of threads in total or number of threads per core. This should be clarified in the column header.

Etoombs (talk) 19:28, 8 May 2013 (UTC)

Separate code/model pages?
Given that we already have a separate Sandy Bridge-E page, and that the preceding few microarchitectures have separate pages for different models (i. e. Bloomfield and Lynnfield for Nehalem), should we also do the same for regular SB, as well as the IB and IB-E?

--Azul120 (talk) 19:56, 19 November 2013 (UTC)


 * That's a good suggestion, but I'd vote for leaving it as-is – it's more compact this way. Just my $.02. :) -- Dsimic (talk) 20:06, 19 November 2013 (UTC)


 * Can we still throw in the processor code tables (i. e. i7-2xxx) inside the main pages?--Azul120 (talk) 04:03, 21 November 2013 (UTC)


 * Having lists of CPU models is bordering with "providing irrelevant content", and those lists in general should be moved into separate articles – such as it's been done with the List of AMD Athlon X2 microprocessors, for example. Though, in case of Intel's various CPU architectures, we already have everything split by architecture, and splitting it further would be really an overkill.  It would be so unreadable and confusing, IMHO.
 * In a few words, I'd say it's Ok to have detailed lists of CPUs in this article.
 * While we're here, what are Ivy Bridge CPU models doing listed in this article? -- Dsimic (talk) 13:46, 21 November 2013 (UTC)


 * That Athlon one is a little different. I was referring to the type of table that lists spec/model ranges, like in the Sandy Bridge-E page. That's why I originally thought of a separate Sandy Bridge code page. As for the IB model listings, I think those are crossposting leftovers. --Azul120 (talk) 21:29, 21 November 2013 (UTC)


 * Hm, if it was up to me, I'd merge content from the Sandy Bridge-E article into Sandy Bridge. The content is quite short, and that way it should be much more readable.  This way it can be easily overlooked.  Just my $0.02, but I might be plain wrong there. :) -- Dsimic (talk) 23:02, 21 November 2013 (UTC)


 * On second thought, it's better to have Sandy Bridge-E as a separate article. We just need to find a way for making it more visible within the Sandy Bridge article.  Thoughts? -- Dsimic (talk) 23:08, 21 November 2013 (UTC)


 * If we're going to do that, we might as well do a separate article for regular Sandy Bridge (microprocessor) as well, using the preceding architecture articles as a reference point. --01:52, 22 November 2013 (UTC)Azul120 (talk)

I'm a bit confused, sorry... Are you referring to something like extracting subsection List of Sandy Bridge processors into a separate article, or to something else? Could, you, please, elaborate a bit? -- Dsimic (talk) 02:53, 22 November 2013 (UTC)


 * I was referring to the type of table on pages like Lynnfield, which is also found on Sandy Bridge-E. — Preceding unsigned comment added by Azul120 (talk • contribs) 08:24, 22 November 2013 (UTC)


 * Ah, that. :) Thanks for the explanation.  Yes, that perfectly makes sense to me, having that kind of a separate Sandy Bridge (microprocessor) article would be really good, and especially useful to readers seeking for quick overviews.  What would be the associated changes to the Sandy Bridge article?
 * Just as a side note, all links to (sub)sections should be using explicit anchors in form of  tags within the titles, as many of those links seem to be broken on the Sandy Bridge-E page, for example.  That way a lot of work remains preserved if/when (sub)sections titles are changed. -- Dsimic (talk) 10:21, 22 November 2013 (UTC)


 * I suppose we could start by finding and confirming any remaining code names and using the template from the Nehalem and Westmere pages, both of which have tables that sort the codes/segments (Sandy Bridge, Sandy Bridge-M, Sandy Bridge-E, etc.) by core count and market segment. --Azul120 (talk) 03:27, 30 November 2013 (UTC)


 * Sounds like a plan to me! At the same time, what would be the associated changes to the Sandy Bridge article? &mdash; Dsimic (talk) 03:31, 30 November 2013 (UTC)


 * No idea, aside from anything I already mentioned (i. e. add the code tables). Perhaps readd the (microarchitecture) to the title. --Azul120 (talk) 06:00, 30 November 2013 (UTC)

Celeron 725C: Just realized I goofed
Spotted a double entry for Celeron 725C, which I have filed under both mobile and server processors. Looking back, I've seen it filed under mobile on the Intel ARK site, yet it has ECC memory as with other Gladden processors. The Pentium 350 was said to be aimed at microservers on other sites despite its desktop categorization on ARK, which I'm sure was in haste since it has never shown up on the main listings since. No such findings yet for the 725C though. Which listing should I leave? — Preceding unsigned comment added by Azul120 (talk • contribs) 21:02, 5 December 2013 (UTC)


 * Hmm, I'd leave it under the mobile processors category, as Celerons in general shouldn't be targeted at the (micro)server market. Just my $0.02. :) &mdash; Dsimic (talk) 01:36, 6 December 2013 (UTC)


 * How about them new Atoms? :P When we do add the separate sub-pages for each of the segments, I'm thinking Gladden should be filed under the non-E pages for SB and IB. --Azul120 (talk) 07:11, 6 December 2013 (UTC)


 * Well, I think you'd agree that confusion on the CPU market is now bigger than ever. :) Ivy Bridge Gladden core is essentially a mobile version of Ivy Bridge, without the integrated GPU, if I'm not mistaken? &mdash; Dsimic (talk) 14:02, 6 December 2013 (UTC)


 * That, and ECC memory. On the i3 and Pentium list pages here, they're also categorized under server chips for some reason. --Azul120 (talk) 20:26, 7 December 2013 (UTC)


 * Maybe because of their support for ECC memory? However, Intel states they're mobile processors. &mdash; Dsimic (talk) 20:38, 7 December 2013 (UTC)


 * Their categorization seems a little random though. The Celeron P1053 (embedded, from the Nehalem generation Jasper Forest) was filed under desktop on the Intel ARK site. Similarly, the i3-2115C is filed under Desktop, while the i3-3115C is filed under Mobile. --Azul120 (talk) 21:35, 7 December 2013 (UTC)