Talk:Static random-access memory

access time
it is stated that SRAM is fast: how many ns does a read take, how many ns does a write takes ? why is DRAM so much slower ?


 * The specific timing will depend on the process, layout, and manufacturer, so there is little that can be said in general. DRAM is slower because of the larger capacitance of the trenched capacitor as opposed to the capacitance on the gates of a few MOSFETs in SRAM.  -- mattb

Look out for possible copyright violations in this article
This article has been found to be edited by students of the India Education Program project as part of their (still ongoing) course-work. Unfortunately, many of the edits in this program so far have been identified as plain copy-jobs from books and online resources and therefore had to be reverted. See the India Education Program talk page for details. In order to maintain the WP standards and policies, let's all have a careful eye on this and other related articles to ensure that no copyrighted material remains in here. --Matthiaspaul (talk) 14:20, 30 October 2011 (UTC)


 * I've run a report. It looks clean today. ~Kvng (talk) 18:18, 24 March 2020 (UTC)

MUX
is requesting a citation for the statement, "data buses are directly accessible rather than multiplexed." with the comment, "You must be kidding me. Any type of memory requires MUX for memory cell selection."

What this is referring to is row/column addressing used by most DRAMs. There is room for improvement here but I don't think the statement is incorrect. We can add a note explaining complexities of DRAM interfaces. We can add a citation substantiating this hobbyist motivation for SRAM. ~Kvng (talk) 15:20, 31 December 2019 (UTC)
 * I would like to see better explanation here. I can't imagine any semiconductor memory device without a multiplexer. Would be nice to a have a citation.  DAVRONOV A.A.  ✉ ⚑ 20:07, 1 January 2020 (UTC)
 * I agree it would be nice to have a citation and I have not removed your request for one. Most SRAMs have a separate pin for each address bit. Most DRAMs use a smaller number of pins for addressing. This is an additional layer of multiplexing. I agree that there is other multiplexing in both types. Using SRAM in electronics projects does simplify things. I have removed, "rather than multiplexed" from the statement. Perhaps this helps. ~Kvng (talk) 23:57, 1 January 2020 (UTC)
 * Thanks. Looks like I'm starting to figure out of which exactly «bus multiplexing» the removed statement was talking about in first place. Read my reply below please if you are interested. DAVRONOV A.A.  ✉ ⚑ 22:28, 30 March 2020 (UTC)

I feel you are talking past each other, because there is two very different kinds of "mux" you are talking about.
 * When bits of data are read out of memory, the memory drives the selected bits onto the data bus. I think we all agree that both DRAM and SRAM do this sort of internal "selection". This kind of internal memory cell selection can be seen as a kind of mux (which may be implemented either a physical mux, or tristate logic).
 * Historically, most SRAM chips and the internal microprocessor SRAM arrays have a separate pin/wire/trace for every logical signal on the system bus -- address pins and data pins; which is conceptually simpler and commonly called "non-multiplexed address bus". Historically, most (all?) DRAM chips re-use pins for different logical signals (at different times) of the system bus, by using "bus multiplexing" (see Bus (computing)). I hope we all agree that a "multiplexed bus interface" at the pins of a chip is different from a "non-multiplexed bus interface" at the pins of a chip. --DavidCary (talk) 22:36, 29 February 2020 (UTC)


 * That's a fine summary. We could put back in a "rather than multiplexed" type of statement with a link to Bus (computing)). I don't mind either way. ~Kvng (talk) 14:33, 3 March 2020 (UTC)
 * I agree. It's fine summary and we can return removed statement back safely by providing the wikilink mentioned above. I think it would be also great to mention that SRAM is typically located on the same die as CPU therefore requiring NO saving space and materials for communication circuitry as it is typically done in off-die non-SRAM implementations by using techniques like bus multiplexing. DAVRONOV A.A.  ✉ ⚑ 22:28, 30 March 2020 (UTC)

India Education Program course assignment
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The above message was substituted from by PrimeBOT (talk) on 19:56, 1 February 2023 (UTC)

WP:PROSE
and have recently created bulleted lists from existing prose. This is not necessarily an improvement. See WP:PROSE. ~Kvng (talk) 16:06, 31 October 2023 (UTC)


 * Please consider the context, though. There are requests to essentially make it more readable and to avoid the writing style of manual. The bullet points that I had applied were with these goals. Starlighsky (talk) 16:13, 31 October 2023 (UTC)
 * It wasn't great prose to being with...but rather it was basically lists written out in the form of sentences. So in this case I do think the bullet points were a slight improvement for readability. But I don't have a strong opinion. Em3rgent0rdr (talk) 16:36, 31 October 2023 (UTC)
 * I'm not suggesting these changes need to be reverted. I just wanted to raise awareness of this WP:MOS point that may not be intuitive to technical people like us who are so used to Powerpoint. ~Kvng (talk) 17:09, 31 October 2023 (UTC)