Talk:Threshold voltage

Vt definition seems to be incorrect
Page 206 of this reputable source seems to be giving a different definition of Vt. http://www.eecs.berkeley.edu/~hu/Chenming-Hu_ch6.pdf Thoughtbox (talk) 19:23, 26 February 2013 (UTC)


 * Hi Thoughtbox! Not getting what you are implying. Are you talking about the "How to Measure the Vt" portion, That is another way to look into the threshold voltage. Industry follows "Maximum gm (Transconductance) method" or "Constant current method" (Mentioned at the end of 206 page). But that doesn't mean that it is in any way giving a different idea of Vt. --Deepon (talk) 10:23, 27 February 2013 (UTC)

Content Written by Anonymous Editor which needs to be structured
Improved/Advanced For above article; note that not the gate voltage but "gate-to-source" voltage is the determinant one. -- For an enhancement type NMOS device, if the gate-to-source voltage is higher than the threshold voltage; there exists enough enough electrons to connect the n+ doped source and drain, and the transistor begins to conduct through from drain to source.

Note that the magnitude of this current is depends on the Vgs (gate - to -drain) voltage. As much the Vgs>Vt higher th current flows.

The simple equation is given below:(For ENHANCEMENT type NMOS device)

Ids = (1/2)Kn(Vgs - Vt)^2       if Vgs-Vt < Vds   and this situation is called SATURATION Mode; Ids = Kn(Vgs -Vt - Vds/2)Vds    if Vgs-Vt > Vds   and this situation is called LINEAR Mode;

Also Threshold is dependent of the bulk-to-source voltage (Vbs). If Vbs=0 it is simply the Vt=Vto defined by the process. But if Vbs is started to increase so the Vt, and Vt!=Vto anymore. There exist also an equation between Vt&Vbs. (Too advanced to give here, but if you like look any Microelectronic Electronics Book)

For a PMOS enhancement type transistor; you need to construct an depletion layer with holes not with the electrons; so you should apply negative voltage to attract holes; which results in a negative Vt. In fact instead of that the convention for PMOS is simply defining Vsg (source to gate voltage) rather than using Vgs. Pls note that he above equations differ for pmos case (look Microelectronic Circuit Design, Jaeger)( Vt<0; VgsVt but Vt<0;) (note the difference between PMOS enhancement) That is, for the NMOS case there is an depletion layer already formed with n doped poly; and for the PMOS case there exists a depletion layer formed with p doped poly.

The threshold voltage varies depending of the device type; and the process. Summary is below.

For enhancement type to be on: NMOS         Vgs>Vt>0; PMOS         0>Vt>Vgs; For depletion Type to be on: NMOS         0>Vt; Vgs>Vt; PMOS         0<Vt; Vgs<Vt;

Tolerance of V_TH
Hello, i've recognized V_TH has a high tolerance range in most datasheet. Is this the general case or just for Power MOSFET? --Biezl (talk) 12:23, 26 July 2008 (UTC)


 * No it's the general case. The knee of a curve is a not so well defined term. that's why.
 * -- Catmangu (talk) 18:59, 13 February 2011 (UTC)

Why restrict to MOSFET?
The idea of a threshold voltage is not unique to MOSFETs. It is a key concept in the understanding of all FETs. This page can definitely use MOSFETs as examples, but it should not be worded to imply that threshold voltage is only used to describe MOSFET behavior. &mdash;TedPavlic (talk) 16:35, 29 January 2009 (UTC)


 * I definitely support TedPavlic! I was really confused reading this. Threshold voltage is a GENERAL term for any diode, transistor (+etc. electric whatever?) where the electric part starts changing its conducting behavior non-linearily.
 * --Catmangu (talk) 18:57, 13 February 2011 (UTC)

Dubious Dependence on temperature
The article seems dubious regarding the dependence of the threshold voltage against temperature. Unfortunately, I'm not sure anymore as it's been years since I worked with them, but I'm still 90% conviced that the threshold rises with the temperature. Otherwise you don't get the linear decrease in performance with increasing temperature. Furthermore, 500mV for a 90nm process is way off. The threshold voltage is lower than that since at least 130nm. If I remember correctly, also 180nm had a lower threshold voltage as it worked bellow 2V. I'll look up my references and update the article.95.76.220.229 (talk) 12:49, 22 January 2015 (UTC)Apass


 * The threshold voltage decreases with temperature. Source: http://www.springer.com/cda/content/document/cda_downloaddocument/9781461407478-c1.pdf?SGWID=0-0-45-1268751-p174130080, from "Managing Temperature Effects in Nanoscale adaptive Systems", ISBN 978-1-4614-0748-5 --Nijoakim (talk) 15:32, 10 March 2015 (UTC)

Removed intro paragraph
Hi guys, there was a paragraph in the intro which was erroneously suggesting that rising Vgs would take an nMOS from off, to linear, to saturation. A rising Vds would do this, if Vgs is above Vth, but a rising Vgs would take an nMOS from off, to saturation, to linear. Not wanting to rewrite the whole paragraph, I just removed it. — Preceding unsigned comment added by 2A02:C7D:BC51:DC00:449F:33CF:48A5:9210 (talk) 10:53, 29 May 2016 (UTC)

Definition of current saturation
The article uses "current saturation". But there is no Wikipedia entry. I can write an article to the topic "current saturation" and "emitter degeneration". Both topics are needed in electronic oscillators that have to produce a sine wave output without too much harmonics.

A good source about these topics is the out-of-print book "Radio Frequency Design" by Wes Hayward.

AndreAdrian (talk) 13:48, 5 July 2016 (UTC)

Pronunciation?
Should one say V T H, or just V T? Thanks, 142.205.202.71 (talk) 15:36, 4 March 2023 (UTC)