Talk:VHDL/to do

(per discussion below)


 * 1) Expand/Clarify difference between VHDL and a software programming language
 * 2) Expand/Clarify difference between synthesizable code and simulation-only code
 * 3) Clarify differences between VHDL revisions ('87, '93, etc.)
 * 4) Revise/Cleanup "Getting started" section
 * 5) Revise/Organize/Trim "Code examples" section
 * 6) Revise/Cleanup the external links
 * 7) Write a NPOV Verilog comparison