Talk:Zero ASIC

Epiphany architecture
I wonder if the epiphany architecture is worth its own page. It has a GGC port, and lots of documentation http://www.kickstarter.com/projects/adapteva/parallella-a-supercomputer-for-everyone/posts/323691 --194.36.2.65 (talk) 14:54, 9 October 2012 (UTC)
 * I do not think that it is necessary to create a page for the architecture of a chip that does not exist. I have not been able to find any independent sources that have actually seen or used any version of an Epiphany processor. Adaptiva's benchmarks, press releases, and product descriptions do little to clear the air of the smell of vaporware. Plus Adaptiva gives so few architectural details that we would find it difficult to scrape together enough facts to create the content for a new article. What few details Adaptiva has released for their architecture does not reveal anything particularly noteworthy or unique. They plan a chip with multiple CPU cores and no cache. If someone can expand on that then I will be surprised. --NoahSpurrier (talk) 16:24, 20 October 2012 (UTC)
 * I think the architecture is the notable thing not the company, that is notable, if it is, only because of the architecture and for Parallella. Now you can buy the chip (in the Parallella) and lots of details are available. Should the name of the article be changed to "Ephiphany (computer architecture)" or something similar and the article turned inside out? I know that notablity in not temporary if you want to add that page and keep this one. I'm not sure two pages are warranted at this point and starting with Adapteva as the notable thing might have just been a mistake. And what about the Parallella, where would that fit? comp.arch (talk) 09:48, 4 November 2013 (UTC)
 * Just as an update, the product as of 2017 has been commercially available for several years now and has support from several developer tools. The Epiphany V product was produced in very limited numbers for benchmarking but while the company remains officially open, further development appears to be a dead issue.
 * I'd still oppose a separate page for the architecture because while the company was and remains important and notable, the ISA is only important as it relates to this particular product. Should another company start making multiprocessor chips that use or draw heavily from this approach, then yeah the ISA becomes notable in itself (indeed potentially more notable than the actual chips). Until then, this page is sufficient. 131.96.47.18 (talk) 13:05, 8 November 2017 (UTC)

LFCS Keynote
At the 2013 Linux Foundation Collaboration Summit, Andreas Olofsson gave a keynote talk about Parallela, a low-cost, low-end implementation of the Eclipse architecture. LWN.net reported on that talk here (non-subscriber link). I guess other trade publications also reported it. Those report(s) would probably be useful in this article, though I'm too busy too edit it myself.

While I'm here, I've removed the Advert tag. This is not the greatest article on Wikipedia, but it is not promotional (and better than many articles ...). Cheers, CWC 13:55, 10 May 2013 (UTC)

Performance
The performance section is embarrassingly opinionated, and totally lacks the critical objective breakdown of information someone actually interested in the performance the Parallella would be looking for. GFLOPS compared to other chips released that year, GFLOPS/$ and GFLOPS/watt are all useful measurements, but this looks like a forum discussion, not objective information. I could also see the same metrics updated to the time of writing being presented (so the Parallella presumably stays the same, but the raw power available from an Intel CPU will scale up. I'd like to blow away the section and more or less rewrite it. I'll dig around for editing etiquette before I pull the trigger, but I'd be happy to take feedback here as well. John Uckele 12:46, 9 July 2015 (UTC)


 * Agreed. Reads like naive marketing hype.  The way I see it, the thing must have an immense von neumann bottleneck; I can't imagine sustained FLOPS being more than 10% of peak flops.  A paragraph on the memory bus architecture would be worth it, and a distinction between peak and sustained flops. 67.198.37.16 (talk) 16:49, 19 September 2015 (UTC)


 * "The way I see it, the thing must have an immense von neumann bottleneck; " the parallela board is indeed bottlenecked by memory, but the processor architecture specifically gets around von-neumann bottleneck with PGAS scratchpads, it's designed for scaling like a supercomputer. infact the new chinese supercomputer chip SW26010 uses a very similar idea. It's hard to program, but very effective when you finally get software tuned for it. The design is really looking forward to future stacked memory, the speculation being the ability to have large amounts of on chip memory tied to each processor- this is the kind of rethink needed as we reach the limits of traditional scaling. Fmadd (talk) 14:00, 21 June 2016 (UTC)

NPOV
Flagged for this statement: "Joel Hruska from Extremetech has the following derogatory opinion about this project". Haven't looked closely if there are any other issues. 84.73.86.81 (talk) 13:18, 21 June 2016 (UTC)

External links modified
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Zeroasic
The company changed its name yet again, now to Zeroasic. --Comrade-yutyo (talk) 23:29, 12 March 2021 (UTC)