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CMOS amplifiers are ubiquitous analog circuits which have been used in smart phones, cameras, telecommunication systems, biomedical circuits, and many other systems, and their performance has great impact on overall specifications of systems. For example, to get higher sensitivity in processing of natural signals(like recorded signal from brain activities, or output of a sensor), we need high performance amplifiers. Usually, in high performance amplifier circuits, transistors are not only used as an amplifier, but also as active loads to achieve higher gain and output swing in comparison with resistive loads.

CMOS technology primarily introduced to design digital circuits, but beside them, analog blocks are also needed to convert natural signals to digital bits. In the last decades, in order to improve speed, power consumption, required area, and other aspects of digital integrated circuits(ICs), the feature size of MOSFET transistors have shrunk(channel length of transistors reduce in newer technologies). This phenomena predicted by Gordon Moore in 1975, which is called Moore’s law, and states that in about each 2 years, the number of transistors doubles for the same silicon area of ICs. Progress in memory design, is an interesting example to see how process advancement have affected it in the last decades. In 1956, a 5MB Hard Disk Drive(HDD) weighted over a tone, while these days having 50000 times more capacity with a weight of several tens of grams is very common.

However, digital ICs benefits from the feature size shrinking, but it has created some difficulties for analog CMOS IC designers. In this article, we will investigate intrinsic gain reduction in analog CMOS amplifiers in newer CMOS technologies which affects the overall gain of amplifiers.Then, we will refer to different methods of amplifier design to overcome this problem. These techniques also create stability issues, which we will also investigate the proposed methods to solve them.

Intrinsic Gain Reduction in Modern CMOS Technologies
Maximum gain of a single MOSFET transistor is called intrinsic gain, and is equal to: $$ Av_{int}=gm\,ro   $$ Which gm is the transconductance, and ro is the output resistance of transistor. As a first order approximation, ro is directly proportional to the channel length of transistors. In a single-stage amplifier, one can increase channel length in order to get higher output resistance and gain as well. But, it will also increase parasitic capacitance of transistor, which will limit the bandwidth of amplifier. Channel length of transistors become smaller in modern CMOS technologies, and makes achieving high gain in single-stage amplifier very challenging. In order to achieve high gain, many techniques have been suggested in the literature. In the following sections, we will have a brief look to different topologies of amplifiers, and their features.

Single-Stage Amplifiers
Telescopic, Folded Cascode(FC), or Recycling FC(RFC) are the most common single stage amplifiers. All these structures use transistors as active loads in order to provide higher output resistance(= higher gain), and output swing. Telescopic amplifier, provides higher gain (due to higher output resistance) and higher bandwidth (due to smaller non-dominant pole at cascode node). In contrast, it has limited output swing and difficulty in implementation of unity-gain buffer. Although FC has lower gain and bandwidth, it can provide higher output swing which is important advantage in modern CMOS technologies, where supply voltage is reduced. Also, since the DC voltage of input and output nodes can be at the same level, it is more suitable for implementation of unity-gain buffer. FC is recently used to implement integrator in a Bio-Nano sensor application. Also, it can be used as a stage in multi-stage amplifiers. As an example, FC is used as the input stage of a two-stage amplifier in designing of a potentiostat circuit, which is to measure neuronal activities, or DNA sensing. Also, it can be used to realize transimpedance amplifier(TIA).TIA can be used in amperometric biosensors to measure current of cells or solutions in order to define the charactristics of a device under test In the last decade, circuit designer have proposed different modified versions of FC circuit. RFC is one of the modified versions of FC amplifier, which provides higher gain, higher bandwidth, and also higher slew rate in comparison with FC(for the same power consumption). Recently, RFC amplifier has used in hybrid CMOS-graphene sensor array for subsecond measurement of dopamine. It is used as a low noise amplifier to implement integrator.

Stability


In many applications, amplifier drives capacitor as a load. In some applications, like switched capacitor circuits,the value of capacitive load changes in different cycles. Therefore, it will affect time constant of output node and the frequency response of amplifier. Stable behavior of amplifier for all possible capacitive loads is necessary, and designer must consider this issue during designing of circuit. Designer should ensure that phase margin(PM) of the circuit will be enough for the worst case. In order to have proper circuit behavior and time response, designers usually consider PM of 60 degrees. for higher values of PM, circuit will be more stable, but it will take longer time for output voltage to reach its final value. In Telescopic, and FC amplifiers, dominant pole is located at the output nodes. Also, there is a non-dominant pole at cascode node. Since capacitive load connected to output nodes, its value will affect the location of the dominant pole. This figure shows how capacitive load affects the location of dominant pole(W1) and stability. Increasing of capacitive load, will move dominant pole toward the origin, and since unity gain frequency(Wunity) is Av(amplifier gain) times of W1, it will also move toward the origin. Therefore, PM will increase, which improves stability. So, if we ensure stability of a circuit for a minimum capacitive load, it will remain stable for larger load values. In order to achieve greater than 60 degrees PM, the non-dominant pole(W2) must be greater than 1.7 times of Wunity.

Multi-Stage Amplifiers
In some applications, like switched capacitor filters or integrators, and different types of analog-to-digital converters, having high gain(70-80dB) is needed, and achieving the required gain sometimes is impossible with single-stage amplifiers. This is more serious in modern CMOS technologies, which transistors have smaller output resistance due to shorter channel length. In order to achieve high gain as well as high output swing, multi-stage amplifiers have invented. To implement two-stage amplifier, one can use FC amplifier as the first stage and a common source amplifier as the second stage. Also, to implement four-stage amplifier, 3 common source amplifier can be cascaded with FC amplifier. It should be mentioned that to drive large capacitive loads or small resistive loads, the output stage should be calss AB. For example, common source amplifier with class AB behavior can be used as the final stage in three-stage amplifier to not only improve drive capability, but also gain. Class AB amplifier can be used as a column driver in LCDs.

Stability in Two-Stage Amplifiers
Unlike single-stage amplifiers, multi-stage amplifiers usually have 3 or more poles and if they used in feedback networks, the closed loop system will probably unstable. In order to have stable behavior in multi-stage amplifiers, it is necessary to use compensation network. The main goal of compensation network is to modify transfer function of the system in such a way to achieve enough PM. So, by the use of compensation network, we should get frequency response similar to what we showed for single-stage amplifiers. In single-stage amplifiers, capacitive load is connected to output node which dominant pole happens there, and increasing its value improves PM. So, it acts like a compensation capacitor (network). To compensate multi-stage amplifiers, compensation capacitor is usually used to move dominant pole to lower frequency in order to achieve enough PM. The following figure shows the block diagram of a two-stage amplifier in fully differential and single ended modes. In a two-stage amplifier, input stage can be a Telescopic or FC amplifier. For the second stage, common source amplifier with active load is a common choice. Since output resistance of the first stage is much greater than the second stage, dominant pole is at the output of the first stage. Without compensation, the amplifier is unstable or at least it does not have enough PM. It is important to mention that the load capacitance will be connected to the output of the second stage, which non-dominant pole happens there. Therefore, unlike single-stage amplifiers, increasing of capacitive load, will move non-dominant pole to lower frequency and will deteriorate PM. Mesri et al. suggested two-stage amplifiers which behave like single-stage amplifiers, and amplifiers remains stable for larger values of capacitive loads. To have proper behavior, we need to compensate two-stage or multi-stage amplifiers. The simplest way for compensation of two-stage amplifier, as shown in the left block diagram of the below figure, is to connect compensation capacitor at the output of the first stage, and move dominant pole to lower frequencies. But, realization of capacitor on silicon chip requires considerable area. The most common compensation method in two-stage amplifiers is Miller compensation (middle block diagram in the below figure.  In this method, a compensation capacitor is placed between input and output node of the second stage. In this case, the compensation capacitor will appear 1+|Av2| times greater at the output of the first stage, and will push the dominant pole as well as unity gain frequency to lower frequencies. Moreover, because of pole splitting effect, it will also move the non-dominant pole to higher frequencies. Therefore, it is a good candidate to make the amplifier stable. The main advantage of Miller compensation method, is to reduce size of the required compensation capacitor by a factor of 1+|Av2|. The issue raised from Miller compensation capacitor is introducing right-half plane(RHP) zero, which reduces PM. Hopefully, different methods have suggested to solve this issue. As an exmaple, to cancel the effect of RHP zero, nulling resistor can be used in series with compensation capacitor (right block diagram of the below figure). Based on the resistor value, we can push RHP zero to higher frequency (in order to cancel its effect on PM), or to move it LHP (in order to improve PM), or even remove the first non-dominant pole to improve Bandwidth and PM. This method of compensation is recently used in amplifier design for potentiostat circuit. Because of process variation, resistor value can change more than 10%, and therefore affects stability. Using current buffer or voltage buffer in series with compensation capacitor is another option to get better results.