User:Asickrishna

Why SystemVerilog for verification SystemVerilog is a rich language that provides constructs needed to support advanced methodologies for verification of today’s complex designs. These methodologies include transaction-based verification (TBV), coverage-driven verification(CDV), Constrained Random testing (CRT), and Assertion Based Verification (ABV). Functional coverage can be further divided into temporal coverage (with SystemVerilog Assertions (SVA)), and data coverage (with covergroup). A good transaction-based verification with CRT relies on constrained randomization of transactions and the channeling of those transactions to transactors for execution (i.e., driving the device under test (DUT) signals for testing). These methodologies can use the collection and access of functional coverage so as to dynamically modify the test scenarios. An adaptation of these methodologies supported by reusable libraries is explained in the book Verification Methodology Manual (VMM) for SystemVerilog [1]. “VMM Standard Library object code is available today for VCS users. VMM Standard Library source code, which can be used with EDA tools compliant with IEEE P1800 SystemVerilog, is planned to be available for license at no additional charge by VCS users and SystemVerilog Catalyst members before the end of the year”, (September 21, 2005).[2]