User:Assassin20X/Computer Architecture



=Computer Architecture & the Fetch Execute Cycle=

Von Neumann Architecture

 * Single Processor
 * Follows a linear sequence
 * Uses one memory for instructions and data

Program Counter (PC)

 * Holds the address of the next instruction
 * Also known as the Sequence Control Register
 * Automatically incremented to point to the next instruction

Memory Address Register

 * Holds the address in memory that data will be read from and written to
 * The contents of the PC are copied to the MAR allowing the PC to be incremented

Current Instruction Register

 * Holds both the operator and the operand of the instruction that is to be executed

Accumulator

 * Stores the results of ongoing calculations

Program Status Register

 * Contains bits that are set or cleared based on the result of a calculation
 * e.g. Carry bit, Overflow/Underflow etc.
 * Controls interrupt flags

Arithmetic & Logic Unit

 * Where data is processed
 * Arithmetic = Addition/Subtraction
 * Logic = Make Decisions
 * Acts as a gateway between the processor and other parts of the computer

Control Unit

 * Fetches Instructions*
 * Decodes Instructions
 * Sends signal to other parts of the computer

Fetch-Decode-Execute Cycle

 * 1) Load the address that is in the PC in to the MAR
 * 2) Increment the Program Counter by 1
 * 3) Load the Instruction in memory into the MDR
 * 4) Load the Instruction in the MDR into the Current Instruction Register
 * 5) Decode the instruction that is in the CIR
 * 6) If the instruction is a jump instruction then :
 * 7) Load the address part of the instruction into the PC
 * 8) Reset by going to step 1
 * 9) Execute the Instruction
 * 10) Reset by going to step 1

'''Steps 1 to 4  = Fetch

'''Steps 5,6a & 7 = Execute

'''Steps 6b and 8 = Reset