User:CTho/Low-k and High-k

After Intel announced their 45nm process with "high-k" and "metal gate", some people seemed to be confused about how high-k related to the "low-k" manufacturers had announced a few years back. Hopefully this will clarify what high-k and low-k mean, and why both are good.

=Capacitance in wires= Between any two conductors you have some "capacitance" which works to keep the voltage between them constant. Imagine two wires running next to each other, both sending a "0" value. If one of the wires switches to sending a "1" value, as it rises towards "1", the other wire will also have its voltage pulled up slightly. If the wire switches back to a "0", the other wire will have its voltage pushed down slightly (below 0 volts). Wires in real circuits are driven by gates, so they will return to their ideal voltage pretty quickly.

Simple analogy
For a more physical way of thinking about capacitance, imagine that wires are rubber tubes and signaling is done with air pressure: high pressure means "1" and low pressure means "0". If you want to run a lot of wires close together, they'll be touching and densely packed. For the sake of the analogy, they're rectangular tubes, and when they're packed, they effectively share walls. See this picture of 3 wires if that isn't clear:

http://ctho.ath.cx/tmp/rubberwires.png

If you are sending a "1" on a wire, the pressure will be high, so its walls will expand outwards slightly, increasing the pressure a little in the neighboring wires.

Wire capacitance in circuits
Often, circuits will have multiple wires running parallel to each other for reasonably long distances so that the wire capacitance between them becomes significant (relative to the capacitance that comes from the gates that the wire is connected to). If you have 3 wires running next to each other currently signaling 0, 1, and 0 and they want to switch to 1, 0, and 1, the capacitance between the wires will mean that while the middle wire is trying to discharge to 0, it's being pulled up on both sides by the outer wires. That slows down the signaling. The outer wires will also be slowed since some of the energy that was intended for raising their voltage gets wasted trying to raise the voltage of the middle wire.

Going back to the analogy, if you're trying to de-pressurize the outer tubes while -pressurizing the middle tube, the two shared walls will bend outwards and it'll take longer than you might have expected to get the pressures fully changed. The picture below should help clarify:

http://ctho.ath.cx/tmp/rubberwires2.png

What "k" is
"k" is a variable in the capacitance equations that represents how strongly one conductor affects conductors around it. A high value of "k" means that each conductor has a strong influence on the conductors around it, while a low value of "k" means that one conductor isn't affected much by others. For wires, this "cross-talk" is a bad thing since it slows down signaling (and, if you're careless in your design, can actually affect functionality).

In the analogy, "k" would be similar to the flexibility of the walls. Flexible walls (high-k) would allow one tube to strongly influence its neighbors (since the walls would bend inwards/outwards a lot), while stiffer walls (low-k) would reduce the effect.

"Low-k" is good for wires.

More on wiring
For power and performance reasons, reducing capacitance between wires is important. If you use a low-k material around the wires, the capacitance will be lower, speeding up the design (and slightly reducing power). However, you could also pack the wires more closely together while maintaining the same capacitance you had before; if you can pack in enough extra wires, you might be able to reduce the total number of layers of metal while maintaining enough wiring tracks for all your signals (I don't know if that's really doable - seems unlikely without an unbelievably awesome k value :)).

=Capacitance in transistors= Take a look at this image:

http://ctho.ath.cx/tmp/simplefet.png

A transistor is a switch that allows or blocks current between the source and drain, based on the voltage at the gate. It works because a voltage on the gate creates an electric field that affects the body, attracting or repelling electrons from the part of the body right below the gate. An extremely simplified explanation of an nmos transistor ("n-type transistor", "nfet") follows. The explanation is simplified to the point of (almost?) being wrong ;). It's really more a way of thinking about it than a description of the physics.

The orange regions are "n-type" silicon, which has an excess of electrons. The green region is "p-type" silicon, which has a shortage of electrons. Current can't flow from from an n-type region to a p-type region for complicated reasons, so normally the transistor will be off (current can't get from either orange region into the green region). However, if you apply a positive voltage to the gate, it will attract electrons to the green region right near the gate. If you attract enough electrons, even though this p-type silicon normally has a shortage of electrons, it will have a surplus, and look sort of like n-type silicon. At that point, since it now looks like there's a path made entirely of n-type silicon, current can flow between the source and drain.

Simple analogy
The analogy is less accurate for transistors than for wires, but I think it's still useful (technically, the pressures would work backwards from the following explanation; this analogy works better for "depletion mode" transistors than "enhancement mode" transistors). Imagine that the body is a narrow channel for water to flow through, and the "gate oxide" is a thin membrane:

http://ctho.ath.cx/tmp/simplefet2.png

If you apply a high water pressure to the gate, the membrane will bend outwards and block off the path through the body so no water can flow between the source and drain. When you apply low pressure to the gate, the membrane won't be in the way, and water can flow between the source and drain easily.

http://ctho.ath.cx/tmp/simplefet3.png

What "k" is
How strongly a voltage on the gate attracts or repels electrons in the body is affected by how well the electric field can get through the gate oxide. The value of "k" represents how well the electric field can get through the gate oxide. A higher "k" means that a small field will control the transistor effectively, whereas with a lower "k", a bigger field is required to control the transistor.

In the water analogy, the "k" value is again the flexibility of the membrane. A high value of "k" means that the membrane would expand easily, whereas with a low "k", it would take more pressure on the gate to block the flow of water in the body.

"High-k" is good for transistor gate oxides.

More on gate oxides
It's nice to have thick gate oxides to reduce leakage power. Quantum mechanical effects cause electrons to jump across very thin gate oxides, and on modern processes, the oxide is thin enough that the flow of electrons can be significant. If you use a higher-k material for the gate oxide, you can get the same transistor performance with a thicker oxide; this thicker oxide will be harder for electrons to jump over, reducing gate leakage. It may also be able to withstand higher voltages without damage.

=Summary= "k" really represents the same quantity in equations for wires and transistor gate oxides, but it's convenient to explain it slightly differently in each situation (at least when trying to write a less-technical explanation!). You want to use high-k materials for the gate oxide and low-k materials between wires.