User:Catccaatt

Xiaomi Mao EDUCATION Drexel University, Philadelphia, PA Master of Science in Engineering, Electrical and Computer Engineering (May 2011) Cumulative GPA: 3.94/ 4.0

Fudan University, Shanghai, China Bachelor of Science, Electronic Engineering (June 2009)  Overall GPA: 3.46/ 4.0

TECHNICAL SKILLS  C, C++, C#, 8086 & MSC-51 Assembler, VBScript, Python, Perl, Turbo Pascal VHDL, Verilog Html MySQL OpenMP, CUDA Matlab, Cadence, Orcad, Synopsys IC compiler, Foundation PROJECTS VLSI Laboratory, Drexel University (Oct, 2009-Present) Clock Mesh Obtained the efficient non-uniform clock mesh by moving register position in a reasonable range. The range is generated by the timing information of the current position. Swapping Cells for Delay Insertion and Power Efficiency Swapped cells from low to high threshold & applied buffers insertion for specific amount of delay insertion, for minimum or subminimum clock period & power efficiency. Explored the trade between number of cells to change and clock period increment. Non-zero Clock Skew Analysis Performed DG algorithm to obtain mean cycle of the circuit network for minimum clock period. Inserted delay to make the clock period feasible. Partitioned large network by CHACO into proper size for LP solver for optimal clock period. Detected cycle and reconvergent path in strongly connected component. Set suitable weight in the network for CHACO to lower iterations in LP solver. Statistical Static Timing Analysis Applied block based algorithm for the slacks of gates analysis. Explored critical paths based on slacks. Optimized the network mapping for speed and cost trade-off on large circuit. Parallel Distributed System Project (Apr, 2010- Jun, 2010) Performed parallel coding on classic algorithms on the platform of clustered computers in distributed system to measure the speed up and bottleneck. PUBLICATION Jianchao Lu, Xiaomi Mao, and Baris Taskin, “Timing Slack Aware Incremental Register Placement with Non-uniform Grid Generation for Clock Mesh Synthesis”, 2011 ACM International Symposium on Physical Design (ISPD), accepted. HONERS/ACTIVITIES Renmin Scholarship for Outstanding Academic Performance, 2nd in Fudan 2006, 2007, 2008 Chinese Mathematical Olympiad, 1st　 in Senior Group China　2004 National Olympiad in Informatics, 2nd in Sichuan Province　 2004 KEY COURSES EDA for VLSI; ASIC Design; Parallel Computing; Data Structure and Algorithm; Research in Computer Engineering; Power System Analysis; Solid State Electronics; Fundamental of System; Digital Signal Processing; Analog/ Digital Logic Electronics; High Frequency Circuit; Computer Architecture Software & Interface Techniques; Probability & Statistics