User:Chinnuskynite

555 Timer :Italic text

General Description :Italic text

The LM555 is a highly stable device for generating accuratetime delays or oscillation. Additional terminals are provided for triggering or resetting if desired. In the time delay mode of operation, the time is precisely controlled by one external resistor and capacitor. For astable operation as an oscillator, the free running frequency and duty cycle are accurately controlled with two external resistors and one capacitor. The circuit may be triggered and reset on falling waveforms, and the output circuit can source or sink up to 200mA or drive TTL circuits.

Features :Italic text

1. Direct replacement for SE555/NE555 2. Timing from microseconds through hours 3. Operates in both astable and monostable modes 4. Adjustable duty cycle 5. Output can source or sink 200 mA 6.  Output and supply TTL compatible 7. Temperature stability better than 0.005% per °C 8. Normally on and normally off output 9. Available in 8-pin MSOP package

Applications :Italic text

1. Precision timing 2. Pulse generation 3. Sequential timing 4. Time delay generation 5. Pulse width modulation 6. Pulse position modulation 7. Linear ramp generator

MONOSTABLE OPERATION :Italic text

In this mode of operation, the timer functions as a one-shot (Figure 1). The external capacitor is initially held discharged by a transistor inside the timer. Upon application of a negative trigger pulse of less than 1/3 VCC to pin 2, the flip-flop is set which both releases the short circuit across the capacitor and drives the output high.The voltage across the capacitor then increases exponentially for a period of t = 1.1 RA C, at the end of which time the voltage equals 2/3 VCC. The comparator then resets the flip-flop which in turn discharges the capacitor and drives the output to its low state. Figure 2 shows the waveforms generated in this mode of operation. Since the charge and the threshold level of the comparator are both directly proportional to supply voltage, the timing interval is independent of supply. During the timing cycle when the output is high, the further application of a trigger pulse will not effect the circuit so long as the trigger input is returned high at least 10μs before the end of the timing interval. However the circuit can be reset during this time by the application of a negative pulse to the reset terminal (pin 4). The output will then remain in the low state until a trigger pulse is again applied. When the reset function is not in use, it is recommended that it be connected to VCC to avoid any possibility of false triggering.