User:Clemenzi/Books/CE PE Exam Study Guide II - Part 2a

Hardware, Programmable Logic, Assembly and Test

 * Hardware
 * Logic family
 * Multi-level cell
 * Flip-flop (electronics)
 * Race condition
 * Binary decision diagram
 * Circuit minimization for Boolean functions
 * Karnaugh map
 * Quine–McCluskey algorithm
 * Integrated circuit design


 * Programmable Logic
 * Standard cell
 * Programmable logic device
 * Field-programmable gate array
 * Complex programmable logic device
 * Application-specific integrated circuit
 * Logic optimization
 * Register-transfer level
 * Floorplan (microelectronics)
 * Hardware description language
 * VHDL
 * Verilog
 * Electronic design automation
 * Espresso heuristic logic minimizer
 * Routing (electronic design automation)
 * Static timing analysis
 * Placement (EDA)
 * Power optimization (EDA)
 * Timing closure
 * Design flow (EDA)
 * Design closure
 * Rent's rule


 * Assembly/Test
 * Design rule checking
 * SystemVerilog
 * In-circuit test
 * Joint Test Action Group
 * Boundary scan
 * Boundary scan description language
 * Test bench
 * Ball grid array
 * Head in pillow (metallurgy)
 * Pad cratering
 * Land grid array