User:Colinshih

CLZ
Counting Leading Zero

IEEE 754 half-precision

 * Binary16

Exponent
exponent = exp + 15 (range: 0~30, 0 for denormalization), Examples:
 * exponent(2-14) = -14 + 15 = 1
 * exponent(20) = 0 + 15 = 15
 * exponent(215) = 15 + 15 = 30

Mantissa

 * Normalization: Most significant 10-digit mantissa
 * de-Normalization: 10-digital mantissa in base of 2-14
 * ex: 2-16 = .01e-14, Mantissa = 10016

Half precision examples
Signbit Exponent10 Mantissa

(largest normal number)
 * 0 3010 11111111112 = 7bff16 = 215 × (1 + (1 − 2−10)) = 65504

(smallest number larger than one)
 * 0 1510 00000000012 = 3c0116 = 1 + 2−10 ≈ 1.001

Verilog-mode

 * Verilog-mode Home
 * Verilog-mode Downloads

.vimrc

 * Emacs verilog-mode autos Plugin

STEP

 * 1) move verilog-mode.el under ~/elisp
 * 2) add (setq enable-local-eval t) to verilog-mode.el::1
 * 3) cp v-emacsauto.vim to ~/emacsauto.vim
 * 4) source emacsauto.vim in .vimrc

How to Use

 * 1) \+d to delete autos
 * 2) \+a to expand autos

Excel to XML
https://www.ibm.com/developerworks/cn/xml/x-tipexc/index.html#artrelatedtopics
 * XML::Excel

Phtyon

 * Example

Immediate
An immediate assertion is a test of an expression the moment the statement is executed SYNTAX: [name:] assert (expression) [pass_statement] [else fail_statement]

Reference

 * 1) https://www.doulos.com/knowhow/sysverilog/tutorial/assertions/
 * 2) https://www.design-reuse.com/articles/10907/using-systemverilog-assertions-in-rtl-code.html
 * 3) http://www.sutherland-hdl.com/papers/2006-DesignCon_Getting_Started_with_SVA_presentation.pdf
 * 4) http://www.cse.scu.edu/~mwang2/verification/Sva.pdf

Examples
To Generate a module: - netlister -gen_module qsx

To Generate a module (and expand the RTL files only): - netlister -gen_module qsx -rtl

To Generate a module (and expand the DV files only): - netlister -gen_module qsx -dv

To expand the DV files only - netlister -gen_tb qsx

To Generate a stubbed module: - netlister -gen_module aca -output_path. -stub

To Generate a stubbed module (without the DV interfaces): - netlister -output_path. -stub -gen_module bax -gen_if 0

To Generate a cluster or the netlist based on an .mrl file (and use all stubbed blocks in a local directory, without generating verification interfaces): - netlister -mrl ${PROJ_SRC_ROOT}/quadpeaks/qua_netlist.mrl -gen_netlist -emacs_expand -use_stubs -output_path. -no_default_libs -gen_if 0

Basic

 * What: High-level synthesis (HLS), sometimes referred to as C synthesis is an automated design process that interprets an algorithmic description of a desired Hardward behavior and creates circuits that implements that behavior.
 * Why: The increasing complexity of logic design in recent decades has forced the methodologies and tools to move to higher abstraction levels. Simulation process in RTL is much inefficient than that in hardware behavior description such as using C for the programming inherent natural.

Deep Learning

 * 莫煩Python:machine-learning

SVM

 * Support Vector Machines

CUDA

 * wiki-CUDA


 * 大學101專題


 * Parallel Vision by GPGPU/CUDA 王元凱


 * 於Win10下安裝TensorFlow並用GPU做加速


 * Windows安装CUDA+TensorFlow教程


 * nVidia How to CUDA c app


 * CUDA的概念及模型, 王建興


 * Unified Memory in CUDA 6


 * An Even Easier Introduction to CUDA

TensorFlow

 * Training a TensorFlow graph in C++ API, Travis - Blog

FMCW

 * The fundamentals of millimeter wave sensors, TI


 * Short-Range Noncontact Sensors for Healthcare and Other Emerging Applications: A Review


 * https://ir.nctu.edu.tw/bitstream/11536/37935/4/250904.pdf


 * https://gb.oversea.cnki.net/KCMS/detail/detail.aspx?filename=1016714738.nh&dbcode=CMFD&dbname=CMFDTEMP


 * https://wenku.baidu.com/view/079194f8c8d376eeaeaa31ac.html


 * Low-Complexity Range-Azimuth FMCW

Depth Imaging

 * 單視域之遞迴式深度估測補償


 * 知乎-結構光原理及3D成像

Verdi
http://www.ictown.com/thread-108024-1-1.html

https://wenku.baidu.com/view/a7a5fcbca32d7375a517800b.html

Async reset
http://www.gstitt.ece.ufl.edu/courses/spring17/eel4712/labs/CummingsSNUG2002SJ_Resets.pdf

MISC

 * Path: analog macro, memory macro...

LEC

 * 1) make script:

How to

 * 1) Create a snapshot
 * 2) Macro EQ?
 * 3) Mapping key point

Introduction

 * Conformal ECO is based on formal EC for finding the NON-EQ key point and internally equivalent point (NET).
 * Benefits:

Flattened Flow

 * Manually ECO for registers changes (added/deleted/renamed)
 * Register D: scan-chain ECO, i.e., bypass D in scan flow. Cell must be kept in the netlist to prevent net re-naming issue by Conformal ECO.
 * Register R: cell rename, but type, netlist must be kept.
 * Register A: dealing with CG*.
 * Copy cells netlist from G2, including clock gating cell (CG*)
 * re-mapping ports .CK, .RB, .D, etc.,.
 * Grep all not-mapped key point to determine what DFF/DLAT should be manually ECOed
 * Run conformal ECO, set flatten model without -GATED_CLOCK.
 * Write ECO design with cell report.

Cons/Pros

 * Because flattened, Conformal ECO not supports automation module-by-module. You may do it by yourself.
 * Be award of clock balancing on added DFF. Flatten model with -NOGATED_CLOCK (default) is suggested.
 * Flattened flow deals with false NON-EQ issue, easy to simply scripts with no boundary constraint.
 * Hier ECO needs add_pin_constraint which could be extracted by analyze hier_compare
 * Flattened flow may generate poor quality of ECO patch.

Some Tips

 * Must using NAME ONLY mapping method to ensure minimal key-point match.
 * Deal with clock gating, use -NOGATED_CLOCK option instead. Otherwise, conformal ECO will replace clock net from middle-tree node.
 * Report unmapped PI/PO
 * Report not-mapped key point

ADiT: Analog/Digital Co-sim
File for ADiT-VPI/ADiT-HDL
 * cosim.f: cosim file list
 * analog.f: include model, etc.
 * analog.scs: analog model
 * cosim.conf: A/D configuration
 * model.lvl3: MOS model file
 * cosim.f.vcs: VCS run arguments
 * vcspli.tab: PLI registration table
 * runvcsaditq: run script for VCS

runvcsaditq spmod.f.vcs

Configuration file

ROM Generation

 * 1) Generate ROM by .xco in the batch mode
 * 2) MIF used for simulation
 * 3) COE used for coregen, and after translating .MIF
 * 4) Flow should be: .XCO+.MIF -> mif2coe -> execute .NGC/.V -> synthesis
 * 5) Files are in SVN: .XCO, .MIF, .V, (.NGC)

.bat

.coe