User:Csuzor/semi yield analysis

Yield and Do

Yield loss definitions

Line Yield, LY, is the fraction of wafers which complete the process flow, from WaferStart to WaferTest, and sometimes to packaged device Test.

Wafer Die Yield, Y, is the fraction of functional devices from the completed wafers, usually measured at WaferTest.

Defect density, Do, is the # of defective die within a fixed area, usually per cm2

E-sort

  E-sort testing  A wafer which has succesfully completed the entire process flow is tested by connecting a probe to the &quot;bond pads&quot;, and running an electrical test program to test the functionality of the die. Dies which fail the test, and which should not be       packaged, are marked with ink. Some products are not tested on the wafer, but are packaged directly and then have a final functionality test. This is often done for small products with high yield, to reduce costs. 

  E-sort tests  Basic tests, including electrical shorts between bond pads, resistivity between bond pads. Functional tests, where a program can simulate the normal functioning of the die, or sometimes to trigger a BIST (Built In Self Test) and obtain a response</li> <li>Leakage tests, where irregular conditions are tested (high voltage pulses), or current flows in stand-by mode</li> <li>The results are placed in &quot;bins&quot;, which can be       analysed to determine the causes of the failures</li> </ul>

<ul> <li> Wafermaps </li> <li>An image of a wafer with the corresponding E-sort fail and pass die shown, is very useful to assist in       determining the potential causes of the failures</li> <li>Images can be stacked, where the images from several wafers are placed on top of each other, and the frequency of the failures for each die position can be represented. </li> <li>The spatial signatures of defective die is often charateristic of a failure mode or a process tool.</li> </ul>

<ul> <li> Bitmaps </li> <li>It is possible to accurately determine the exact location of the failures on memory segments, by determining which Bit Lines and Word Lines are involved.</li> <li>Analysis tools are now available which then enable a FIB to be made and subsequent SEM analysis can reveal the exact cause of the failure.</li> </ul>

Die Yield

<ul> <li> The models </li> <li>Poisson model, which assumes that random defects are entirely independent</li> <li> Y = M.exp(-A.Do) </li> <li>Negative binomial model, which uses a clustering factor to describe to which degree random defects are clustered together</li> <li> Y = M / (1 + A.Do / a)a </li> </ul>

<ul> <li>Seeds model, which is a special case of the negative binomial model, where the clusering factor is 1</li> <li> Y = M / (1 + A.Do ) </li> </ul>

<ul> <li>M is a factor which represents systematic yield losses. It represents the situation where Do tends to zero (no       defects), and thus the maximum yield.</li> <li>A is the area of the die, in the same units as Do, the number of defective die per area.</li> <li>a is the clustering factor, used to evaluate the degree of clustering of the defects</li> </ul>

<ul> <li> Understanding Do    </li> <li>Do is normally reported as # defective die per cm^2. This is one of the most important fab performance indicators, since it indicates the quality of the fab and the process.</li> <li>Do determines the yield which can be achieved with different product die sizes (the larger the product die,       the smaller the % of good die)</li> <li>Do is also called the &quot;random defectivity parameter&quot;, since in general the position on the wafer where good and bad die will be located is random. Positions where it is known that all wafers will have failing die are called &quot;systematic failures&quot;, and these are represented by M.</li> </ul>

<ul> <li> Understanding M    </li> <li>Potential Good Die per Wafer, PGDW, enables a good estimation of the # of die which may show yield on a       wafer.</li> <li> </li> <li>where the constant is specific for the wafer size and shape. The second term represents the loss of yield from wafer edge effects.</li> <li>A good starting point for determining M is to assume that</li> <li> M = Mo = #_tested_Die / PGDW </li> <li>M will always be bigger than Mo, and the extra factor will be related to systematic faults.</li> <li>From a wafer map showing the good and failed die, it       possible to determine M. Simply by grouping the die into groups of 2, 4, 8, 16, and counting the yield fraction of       these &quot;larger&quot; die, and plotting as shown below, an extrapolation to very small die size will reveal M.</li> </ul>

Fault mechanisms

<ul> <li> Defectivity </li> <li>Defects are usually particles or unwanted material placed on the wafer during the processing through the fab. The size, location, material, and originating process level of these defects will determine the probability whether it will affect yield or not.</li> <li>Below is a chart which shows the Yield loss with single process step defectivity incidents, compared to       &quot;normal defectivity&quot; levels for this step. This Yield loss is dependent on the product die size.</li> </ul>

<img src="images/yield_die_size.gif" width="506" height="325">

<ul> <li>Below is a chart which shows the yield loss expected for different type of typical defectivity incidents. The incidents are identified as FE (Front End processing), Contact processing, BE (Back End processing), and the yield loss depends on the die size. The baseline performance is also shown, where no real incidents exist, but the yield is dependent on the &quot;normal&quot; defectivity level of the fab.</li> </ul>

<img src="images/yield_incidents.gif" width="521" height="315">

<ul> <li> Parametric </li> <li>Parametric yield loss is caused by a mismatch between the process and the product design.</li> <li>Mistakes in design or design rules, can lead to wafers which have been processed correctly, but have low Die Yield because the electrical parameters are not as       expected.</li> <li>Some examples are:</li> <li>Product dependent yield loss, from incorrect design rules. eg. Incorrect Vt caused by dopant diffusion.</li> </ul>

<ul> <li> Systematic </li> <li>Systematic yield loss is caused by repetitive equivalent defects, either at the same place on every or alternate die, or at the same place on every or alternate wafer, or       on each lot.</li> <li>Some examples are:</li> <li>Photolithography reticle problems. eg. Yield loss on 1 out of 9 die, from particle on 1 reticle</li> <li>Design related faults, causing particular defects modes. eg. CMP macro-loading, SOG related stringers</li> <li>Wafer edge problems. eg. cracking of highly stressed oxide layers</li> </ul>

Defectivity control

<ul> <li>Numerous metrology equipment are available to quantify the number, size and type of defects found on wafers.</li> </ul>

<ul> <li> Off-line </li> <li>Used for controlling the defect performance of process equipment, special tests with non-production wafers are made, and inspected.</li> </ul>

<ul> <li> In-line </li> <li>Wafer inspections are made on production wafers. Useful for controlling the defect performance of several equipment at the same time, for controlling the quality of the production wafers, and for checking on potential process problems only visible during sequential processing.</li> </ul>

<ul> <li> In-situ </li> <li>Not a direct measure of defects on wafers, but a       measurement of the cleanliness of the wafer processing areas of the equipment, during wafer processing. Useful for predicting problems before they can be seen on the wafers.</li> </ul>

<ul> <li>Total Defect Density</li> <li>Declustered Defect Density</li> <li>Added Defect Density</li> <li>Specific Defect Density</li> <li>Kill Ratio</li> <li>Defect size distribution</li> </ul>

Sampling plans

<ul> <li>Since it is very expensive to inspect all products, there are a number of techniques to optimize the effective detection and reaction to process and equipment problems.</li> </ul>

<ul> <li> Process sampling </li> <li>It is often sufficient to control the defectivity level of the production lots at a few positions within the entire flow, since defects which are added to the wafer will often be visible several process steps later. Several factors need to considered.</li> <li>The delays in detecting a problem with one equipment depends on the position of the equipment and the next inspection step.</li> <li>Defects generated at some steps may seem very large or       very small, but their impact on the Die Yield may be        difficult to estimate because further processing steps may eliminate them or may cause them to grow into larger Die Yield limiting defects.</li> </ul>

<ul> <li> Front End </li> <li>Often the following process levels are chosen for defectivity inspections:</li> <li>Capacitor, after completion (DRAM)</li> <li>Active, after LOCOS or after STI</li> <li>Poly, after Poly etch</li> <li>Spacer, after Spacer etch</li> <li>Salicide, after completion</li> </ul>

<li> Back End </li> <li>Dielectric, after planarization</li> <li>Contact, after contact fill</li> <li>Metal layer, after metal etch or metal CMP</li> <li>Inter Metal Dielectric, after Planarisation</li> <li>Via, after via fill</li> <li>Previous 3 inspection steps can be repeated for each metal layer, although if the equipment used for each layer is identical then it is only necessary to inspect 1 of each to control the equipment quality</li> <li>Pad, after bond pad opening</li>

<ul> <li> Product sampling </li> <li>In fabs where a large number of products are processed, it is important to choose to inspect products which are processed in large volumes for long periods. This will ensure that good historical trending is possible.</li> </ul>

<ul> <li> Lot sampling </li> <li>Instead of inspecting every lot, and limiting the number of nspection steps in the process flow, it is better to       inspect a fraction of all lots (from one or more product        types), and monitor the same lot at each inspection step throughout the process flow. This will ensure that a       proper analysis of the origin of the defects is possihle.</li> </ul>

<ul> <li> Wafer sampling </li> <li>Again to reduce the # of inspections required, it is       possible to select specific wafers to inspect from the lots to be inspected. It is thus important to select the same wafers at each inspection step in the process flow. The choice of wafers to inspect should be done by       considering the processing order through the equipment, and in particular, to select at least 1 wafer from each process chamber on cluster equipment, to ensure that a       'bad&quot; chamber would be detected from the defectivity inspections.</li> </ul>

<ul> <li> Die sampling </li> <li>Often poorly used, Die sampling allows increases in       throughput on lengthy inspection steps, by selecting only a fraction of the total die on the wafer, or by selecting to inspect only a fraction of each die, usually where the density of the structures is highest. A common choice is       to inspect the memory components, which are very sensitive to defects, and from which bit-mapping may be       possible later.</li> </ul>

SPC

<ul> <li>Process capability</li> <li>UCL, LCL, USL, LSL</li> <li>Cp, Cpk</li> <li>Determining the Control Limits</li> <li>OOC, OCAP</li> <li> SPC rules : Several options are well known for placing checks on data trends. Below are shown 8 common tests, which can be used to determine whether equipment is under statistical control, and which are usually activated such that the system will be       automatically stopped when they occur.</li> </ul>

<img src="images/SPC.gif" width="526" height="617">

Statistical Analysis

<ul> <li>Good / Bad Commonality</li> <li>Cumulative Probability</li> <li>Continuous Parameter</li> <li>Correlation</li> </ul>

Yield management

<ul> <li>Low yielding wafers and Reliability</li> <li>The impact of Defectivity on Yield</li> </ul>

<ul> <li> Defect Size distribution </li> <li>The statistical distribution of defect sizes is usually found to be:</li> <li> Number of defects is proportional to 1 / rp       , where p = 2 to 3</li> <li>If p &lt; 3, then there are large numbers of large defects</li> <li>If p = 3, then there are equally distributed numbers of       small and large defects</li> <li>If p &gt; 3, then there are large numbers of small defects</li> </ul>

<ul> <li> Kill ratio </li> <li>The Kill ratio of a defect type, or a defect inspection, is defined as the ratio of the Die Yield difference between die without defects and die with 1 or more defect.</li> <li>If Die Yield of die without defects is 90%, and the Die Yield of die with defects is 45%, then the kill ratio is       50%.</li> <li>For each inspection step in the process flow, a Kil ratio can be calculated, as show below.</li> </ul>

<img src="images/Kill_ratio.gif" alt="Kill Ration per Process Step" width="506" height="333">

<ul> <li> Yield impact Pareto </li> <li>The definition of the Killing ratio is such that is is       possible to estimate the Die Yield loss from each inspection step, using the defectivity yield correlation</li> <li> Y = 1 / (1 + Kr.A.Dd / a)a </li> <li> where Kr is the Killing ratio of the defect types (averaged for each inspection step), A the Area of the Die, Dd is the Defect density, and a is the clustering factor of the defects at each inspection. </li> </ul>

<img src="images/yield_kill_ratio.gif" alt="cumulative Yield by Kill Ratio" width="505" height="333">

<ul> <li> Yield trend on wafer </li> <li>The trend of the yield on concentric rings of the wafer, can help to determine the causes of problems in a fab. This can be done by plotting the yield of die within annular rings on the wafer. (example. the % good die in       each area of the wafer between a radius x and x+1 from        the center)</li> <li>In the chart below 2 problem areas are seen: 1. In the center of the wafer low yield is seen, 2. At a radius of       3.0 to 4.0 cm low yield is seen, 3. The fall-off of yield at the edge of the wafer begins from 8.5cm, which is       large compared to the industry accepted process specifications with only 3-6mm of edge exclusion.</li> <li>By plotting the cummulative yield (taking into       consideration the # of die and the yield for each area), it is possible to compare diferent data, for example to       identify problem wafers / lots / or periods of        manufacturing.</li> </ul>

<img src="images/yield_rings.gif" width="504" height="314">

<ul> <li> Critical Area </li> <li>The critical area of a die is the area within which a       particle, defined by a specific size and shape, will cause a failure of the die. Expressed as a percentage of       the total die area, it is clear that the critical area will increase with larger particle sizes.</li> <li>Defect size distributions, represented by the blue line, are important in determining the expected yield. An       unusual distribution of defects, for example many more small defects than normally expected, can cause low yields in products with smaller dimensions, such as in a       newer technology.</li> </ul>

<img src="images/yield_critical_area.gif" alt="Cumulative Yield by defect size, critical area" width="497" height="319">

<ul> <li> Yield Improvement learning curve </li> <li>As the # of wafers processed increases for a new fab or       new process, then a typical yield improvement curve is        seen, as below.</li> </ul>