User:Dguisinger/Blazefx

The BlazeFX is a programmable DSP architecture developed by ModularLogix specifically targeted for field programmable gate array (FPGA) signal processing applications. The BlazeFX core is available in 16-bit, 32-bit and 48-bit versions.

The BlazeFX architecture is licensable.

Architecture
The BlazeFX utilizes a dual-harvard architecture. There are three external data-busses. Program memory, Bus-A, and Bus-B.

RISC Features

 * No support for misaligned memory accesses
 * Uniform 16 x 16-bit, 16x32-bit, or 16x48-bit [register file].
 * Fixed instruction width of 36-bits designed to make efficient use of Xilinx BlockRAM memory and ease decoding.
 * Conditional execution on most instructions reducing branch overhead
 * 16-result addressable shift register for storing ALU results
 * Dual independent data memory busses with inline-address incrementation bits in instruction code

Conditional Execution
The BlazeFX has a conditional execution feature on every instruction. Most CPUs only have condition codes on branch instructions.

Pipelining
The results from the ALU in the BlazeFX are stored in a 16-deep shift-register. This shift-register is the same width as the particular BlazeFX architecture in use. This register is directly addressable in all instructions accepting OPERAND B, allowing the ALU results to be held until needed and effectively expanding the total user-registers to 32. Since the user can start-and-forget an ALU operation with the results ending up in the result shift-register, an additional bit is made available in the instruction opcode to execute in Turbo Mode. Turbo Mode executes one instruction after the next, without waiting for the result to become available allowing the user to specify pipelining in the most optimal locations (such as Multiply-Accumulate loops).