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Continuation of ANALOG TO DIGITAL CONVERTER :

ADC structures:

These are the most common ways of implementing an electronic ADC:

A direct conversion ADC or flash ADC A successive-approximation ADC A delta-encoded ADC A ramp-compare ADC (also called integrating, dual-slope or multi-slope ADC) A pipeline ADC (also called sub ranging quantizes) A Sigma-Delta ADC (also known as a Delta-Sigma ADC)

Today we will discuss Direct method & Successive methods

• A direct conversion ADC or flash ADC :

It has a comparator that fires for each decoded voltage range. The comparator bank feeds a logic circuit that generates a code for each voltage range.

Direct conversion is very fast, but usually has only 8 bits of resolution (256 comparators) or fewer, as it needs a large, expensive circuit.

ADCs of this type have a large die size, a high input capacitance, and by outputting an out-of sequence code. They are often used for video or other fast signals.

• A successive-approximation ADC :

The way successive approximation works is through constantly comparing the input voltage to the output of an internal DAC (fed by the current value of the approximation) until the best approximation is achieved.

At each step in this process, a binary value of the approximation is stored in a successive approximation register (SAR). The SAR uses a reference voltage (which is the largest signal the ADC is to convert) for comparisons.

For example if the input voltage is 60V and the reference voltage is 100V, in the 1st clock cycle, 60V is compared to 50V (the reference, divided by two. This is the voltage at the output of the internal DAC when the input is a '1' followed by zeros), and the voltage from the comparator is positive (or '1') (because 60V is greater than 50V).

At this point the first binary digit (MSB) is set to a '1'. In the 2nd clock cycle the input voltage is compared to 75V (being halfway between 100 and50V: This is the output of the internal DAC when its input is '11' followed by zeros) because 60V is less than75V, the comparator output is now negative (or '0'). The second binary digit is therefore set to a '0'.like that 3rd clock,etc...

This is also called bit-weighting conversion, and is similar to a binary search. The analogue value is rounded to the nearest binary value below, meaning this converter type is mid-rise. Because the approximations are successive.

"The conversion takes one clock-cycle for each bit of resolution desired. The clock frequency must be equal to the sampling frequency multiplied by the number of bits of resolution desired".

For example, to sample audio at 44.1 kHz with 32 bit resolution, a clock frequency of over 1.4 MHz would be required. ADC' s of this type have good resolutions and quite wide ranges. They are more complex than some other designs.http://www.facebook.com/Epistemesoft