User:Ghzclk

Ghzclk is a Wikipedia user with expertise in microprocessor global clock distribution network design and tools. This includes design, modeling, and optimization, of lossy on-chip transmission-lines. Ghzclk (talk) 16:16, 10 May 2009 (UTC)

Here is a working document which I may add to the Clock_distribution_network page.

Motivation
For many applications the ideal clock signal is a perfectly periodic signal, with 50% duty cycle. Most clock and logic circuits on a processor perform no energy recycling. The energy required to charge a capacitor C to voltage Vdd (chip power supply voltage) is CV2. Without energy recycling, the energy to charge a circuit node to Vdd is converted to heat in the wires and devices of the processor. In virtually all commercial processors, the parasitic capacitance of wires in the global clock distribution. . . ?????

Switching Capacitors Without Resonanct Circuit
When any node in a chip transitions from a logical 0 to a logical 1, all the parasitic (unavoidable) device and wire capacitance associated with this node C is charged up to the power-supply voltage V when a logical 1 is desired, consuming energy CV2. Then when a logical 0 is desired, these capacitances are discharged to the power supply ground through devices and wire resistances that turn the energy CV2 irreversibly into heat in the devices and wires on the chip. Most circuit nodes on a microprocessor switch less than 5% of the cycles (defined as a switching factor of 5%), while ungated clock signals must generally switch twice per cycle, every cycle (defined as a switching factor of 200%), consuming significant power.

Clock Gating
This section will be used to supplement the discussion of Clock Gating:

Ungated clock signals switch twice per cycle, consuming significant chip power, even when the circuits being clocked are performing no useful purpose. Every latches or flip-flops must recieve the clock signal every cycle, in case the data stored in the latch is supposed to change. However, in current processors, it is rare for more than 5% of the latches in a processor to actually change in any cycle. While clock gating can reduce this power, it can be difficult to design the circuit needed to predict when a particular set of latches can have their clock signals gated. In addition, this clock gating circuitry requires chip area, and can consume more power than is saved by clock gating.