User:HRShami/Ozgur Sinanoglu

Ozgur Sinanoglu is a Turkish electrical engineer, academic and researcher. He is the Associate Dean of Engineering and Professor of Electrical and Computer Engineering at New York University Abu Dhabi. He is the director of the Design-for-Excellence Lab at NYU Abu Dhabi. He is also a Research Associate Professor of at New York University Tandon School of Engineering.

His primary field of research is the reliability and security of integrated circuits, mostly focusing on CAD tool development. Sinanoglu's research is focused on. His work deals with Design-for-Testability, Design-for-Trust and Design-for-Excellence. He has published over 170 papers and holds 19 patents. His research has been funded by US National Science Foundation, US Department of Defense, Intel Corporation, Semiconductor Research Corporation, and Mubadala Technology.

Education
Sinanoglu received a B.S. in Computer Engineering and a B.S. in Electrical and Electronics Engineering, both from Bogazici University in 1999. He then moved to the United States where he received an M.S. in Computer Engineering in 2001 and later a Ph.D. in Computer Engineering in 2004 from University of California, San Diego. During his Ph.D., he won the IBM PhD fellowship award twice.

Career
After completing his Ph.D., Sinanoglu joined Qualcomm CDMA Technologies as a Senior Design and Test Engineer, primarily responsible for developing cost-effective test solutions for low-power SOCs. In 2006, he left Qualcomm to join the Kuwait University as Assistant Professor of Mathematics and Computer Science. In 2010, he moved back to Abu Dabhi where he started teaching at the New York University Abu Dabhi. At the same time, he also took up the position of Research Assistant Professor of Electrical and Computer Engineering at New York University Polytechnic School of Engineering, becoming Global Network University Associate Professor in 2014 and Full Professor in 2018.

In 2016, Sinanoglu was appointed as the Associate Dean of Engineering at New York University Abu Dhabi.

Sinanoglu has been an Associate Editor of Journal of Electronic Testing: Theory and Applications since 2015. He was the Associate Editor of Microelectronics Journal (2014-2015), of IEEE Transactions on Information Forensics and Security (2014-2017).

Research and work
Sinanoglu's research been focused on designing integrated circuit chips with built-in defense mechanisms in order to expose any intentional malicious alteration of the chips and protect design IP from reverse engineering and side-channel attacks. He, along with the members of his lab have developed Design-for-Excellence techniques comprising hardware design blocks and accompanying software CAD tools.

Awards and honors

 * 2009 - Faiza Al-Kharafi Research Award, Kuwait University
 * 2009, 2010 - Best Young Researcher Award, Kuwait University
 * 2011 - Best Paper Award, VLSI Test Symposium

Books

 * Trustworthy Hardware Design: Combinational Logic Locking Techniques (2019)

Book chapters

 * Hardware Security and Trust: Logic Locking as a Design-for-Trust Solution: Design and Implementation. In: The IoT Physical Layer. (2018)
 * Physical Unclonable Functions and Intellectual Property Protection Techniques. In: Fundamentals of IP and SoC Security. (2015)
 * New Scan-Based Attack Using Only the Test Mode and an Input Corruption Countermeasure. In: VLSI-SoC: At the Crossroads of Emerging Trends. VLSI-SoC (2013).

Selected articles

 * Sinanoglu, O., Bayraktaroglu, I., & Orailoglu, A. (2002). Test power reduction through minimization of scan chain transitions. Proceedings 20th IEEE VLSI Test Symposium (VTS 2002).
 * Rajendran, J., Jyothi, V., Sinanoglu, O., & Karri, R. (2011). Design and analysis of ring oscillator based Design-for-Trust technique. 29th VLSI Test Symposium.
 * Rajendran, J., Pino, Y., Sinanoglu, O., & Karri, R. (2012). Security analysis of logic obfuscation. Proceedings of the 49th Annual Design Automation Conference on - DAC 12.
 * Rajendran, J., Pino, Y., Sinanoglu, O., & Karri, R. (2012). Logic encryption: A fault analysis perspective. 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).
 * Rajendran, J., Sam, M., Sinanoglu, O., & Karri, R. (2013). Security analysis of integrated circuit camouflaging. Proceedings of the 2013 ACM SIGSAC Conference on Computer & Communications Security - CCS 13.
 * Kannan, S., Rajendran, J., Karri, R., & Sinanoglu, O. (2013). Sneak-Path Testing of Crossbar-Based Nonvolatile Random Access Memories. IEEE Transactions on Nanotechnology, 12(3), 413–426.
 * Rajendran, J., Sinanoglu, O., & Karri, R. (2014). Regaining Trust in VLSI Design: Design-for-Trust Techniques. Proceedings of the IEEE, 102(8), 1266–1282.
 * Rajendran, J., Zhang, H., Zhang, C., Rose, G. S., Pino, Y., Sinanoglu, O., & Karri, R. (2015). Fault Analysis-Based Logic Encryption. IEEE Transactions on Computers, 64(2), 410–424.
 * Yasin, M., Mazumdar, B., Rajendran, J. J. V., & Sinanoglu, O. (2016). SARLock: SAT attack resistant logic locking. 2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST).
 * Yasin, M., Sengupta, A., Nabeel, M. T., Ashraf, M., Rajendran, J. (J., & Sinanoglu, O. (2017). Provably-Secure Logic Locking. Proceedings of the 2017 ACM SIGSAC Conference on Computer and Communications Security - CCS 17.